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Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) (2000)
Berkeley, California
Nov. 8, 2000 to Nov. 10, 2000
ISBN: 0-7695-0786-7
pp: 47
B. Vermeulen , Philips Res. Lab., Eindhoven, Netherlands
G.J. van Rootselaar , Philips Res. Lab., Eindhoven, Netherlands
ABSTRACT
For today's multi-million transistor ICs, existing design verification techniques cannot guarantee that first silicon is designed error free. Because of this reality, there is a need for a good debug methodology. This paper describes the application of a generic silicon debug methodology to a modular video-processing chip called co-processor array (CPA). The debug hardware, which was added to the design, and the supporting debugger software are described. The application of the added debug functionality and its effectiveness during first silicon bring-up are also presented.
INDEX TERMS
computer debugging; coprocessors; silicon debug; coprocessor array; video applications; design verification; debug methodology; generic silicon debug methodology; modular video-processing chip; debugger software
CITATION

G. van Rootselaar and B. Vermeulen, "Silicon debug of a co-processor array for video applications," Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)(HLDVT), Berkeley, California, 2000, pp. 47.
doi:10.1109/HLDVT.2000.889558
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