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30th Hawaii International Conference on System Sciences (HICSS) Volume 1: Software Technology and Architecture (1997)
Maui, Hawaii
Jan. 3, 1997 to Jan. 6, 1997
ISSN: 1060-3425
ISBN: 0-8186-7743-0
pp: 566
M. A. Thornton , University of Arkansas
D. L. Andrews , University of Arkansas
ABSTRACT
This paper describes a method of analysis for detecting and minimizing memory latency using a directed data dependency graph produced from a compiler. These results are applicable to the development of methods for the optimal generation of instruction threads to be executed on a multi-threaded, datadriven architecture. The resulting runtime reductions are accomplished by minimizing memory access times by individual processing elements. Additionally, these analysis methods can be used to predict measures of achievable parallelism for a given program graph which can be exploited by a reconfigurable, multi-threaded architecture.
INDEX TERMS
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CITATION

D. L. Andrews and M. A. Thornton, "Graph Analysis and Transformation Techniques for Runtime Minimization in Multi-Threaded Architectures," 30th Hawaii International Conference on System Sciences (HICSS), Maui, Hawaii, 1997, pp. 566.
doi:10.1109/HICSS.1997.667356
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