The Community for Technology Leaders
2014 47th Hawaii International Conference on System Sciences (1995)
Hawaii, USA
Jan. 4, 1995 to Jan. 7, 1995
ISSN: 1060-3425
ISBN: 0-8186-6930-6
TABLE OF CONTENTS
High Performance Computing and I/O Systems

Introduction (PDF)

pp. 3

Performance tuning of a multiprocessor sparse matrix equation solver (PDF)

K.Y. Wu , Dept. of Electron. Eng., City Polytech. of Hong Kong, Kowloon, Hong Kong
R.M.M. Chen , Dept. of Electron. Eng., City Polytech. of Hong Kong, Kowloon, Hong Kong
A.M. Layfield , Dept. of Electron. Eng., City Polytech. of Hong Kong, Kowloon, Hong Kong
P.K.H. Ng , Dept. of Electron. Eng., City Polytech. of Hong Kong, Kowloon, Hong Kong
X.D. Jia , Dept. of Electron. Eng., City Polytech. of Hong Kong, Kowloon, Hong Kong
pp. 4

Architectural synthesis with possibilistic programming (PDF)

I. Karkowski , Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 14

An implementation of hash based ATM router chip (PDF)

V. Milutinovic , Sch. of Electr. Eng., Belgrade Univ., Serbia
E. Jovanov , Sch. of Electr. Eng., Belgrade Univ., Serbia
A. Janicijevic , Sch. of Electr. Eng., Belgrade Univ., Serbia
D. Raskovic , Sch. of Electr. Eng., Belgrade Univ., Serbia
pp. 32

Optimized mapping of video applications to hardware-software for VLSI architectures (PDF)

C.H. Gebotys , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
R.J. Gebotys , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 41

Performance analysis of RAID-5 disk arrays (PDF)

O.A. Panfilov , NCR Corp., Colorado Springs, CO, USA
pp. 49

Correlation of the paging activity of individual node programs in the SPMD execution mode (PDF)

D.C. Marinescu , Dept. of Comput. Sci., Purdue Univ., West Lafayette, IN, USA
Kuei Yu Wang , Dept. of Comput. Sci., Purdue Univ., West Lafayette, IN, USA
pp. 61
Reflective Memory and Distributed Shared Memory Architectures for OLTP

Introduction (PDF)

pp. 72

A survey of distributed shared memory systems (PDF)

V. Milutinovic , Sch. of Electr. Eng., Belgrade Univ., Serbia
M. Tomasevic , Sch. of Electr. Eng., Belgrade Univ., Serbia
J. Protic , Sch. of Electr. Eng., Belgrade Univ., Serbia
pp. 74

Reflective-memory multiprocessor (PDF)

S. Lucci , Dept. of Comput. Sci., City Univ. of New York, NY, USA
A. Gupta , Dept. of Comput. Sci., City Univ. of New York, NY, USA
I. Gertner , Dept. of Comput. Sci., City Univ. of New York, NY, USA
U. Hegde , Dept. of Comput. Sci., City Univ. of New York, NY, USA
pp. 85

Pentium MPP for OLTP applications (PDF)

M. Natale , Encore Comput. Corp., Fort Lauderdale, FL, USA
M. Baker , Encore Comput. Corp., Fort Lauderdale, FL, USA
D. Wilson , Encore Comput. Corp., Fort Lauderdale, FL, USA
I. Gertner , Encore Comput. Corp., Fort Lauderdale, FL, USA
S. Lucci , Encore Comput. Corp., Fort Lauderdale, FL, USA
R. Collins , Encore Comput. Corp., Fort Lauderdale, FL, USA
pp. 95

Fault-tolerant disk storage and file systems using reflective memory (PDF)

N. Vekiarides , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 103

Application-transparent checkpointing in Mach 3.O/UX (PDF)

Z. Segall , Dept. of Comput. & Inf. Sci., Oregon Univ., Eugene, OR, USA
M. Russinovich , Dept. of Comput. & Inf. Sci., Oregon Univ., Eugene, OR, USA
pp. 114

MPP UNIX enhancements for OLTP applications (PDF)

G. Schaffer , Encore Comput. Corp., Marlborough, MA, USA
pp. 124

A distributed lock manager on fault tolerant MPP (PDF)

M. Aldred , Encore Comput. Corp., Marlborough, MA, USA
I. Gertner , Encore Comput. Corp., Marlborough, MA, USA
S. McKellar , Encore Comput. Corp., Marlborough, MA, USA
pp. 134

Tuning Oracle7 for nCUBE (PDF)

G. Arnaiz , Oracle Corp., Redwood Shores, CA, USA
pp. 137

A simulation-based comparison of two reflective memory approaches (PDF)

M. Tomasevic , Sch. of Electr. Eng., Belgrade Univ., Serbia
M. Jovanovic , Sch. of Electr. Eng., Belgrade Univ., Serbia
V. Milutinovic , Sch. of Electr. Eng., Belgrade Univ., Serbia
pp. 140
Instruction Level Parallelism

Introduction (PDF)

pp. 151

An architecture for high instruction level parallelism (PDF)

S. Duvvuru , Sun Microsyst. Inc., Mountain View, CA, USA
H. Sachs , Sun Microsyst. Inc., Mountain View, CA, USA
S. Arya , Sun Microsyst. Inc., Mountain View, CA, USA
pp. 153

The architecture of an optimistic CPU: the WarpEngine (PDF)

J.G. Cleary , Dept. of Comput. Sci., Waikato Univ., Hamilton, New Zealand
H. Kinawi , Dept. of Comput. Sci., Waikato Univ., Hamilton, New Zealand
M. Pearson , Dept. of Comput. Sci., Waikato Univ., Hamilton, New Zealand
pp. 163

Evaluation of a branch target address cache (PDF)

S. Arya , Sun Microsyst. Inc., Mountain View, CA, USA
S. Duvvuru , Sun Microsyst. Inc., Mountain View, CA, USA
pp. 173

An improved dynamic register array concept for high-performance RISC processors (PDF)

M. Schafers , Dept. of Design of Integrated Circuits, Tech. Univ. Braunschweig, Germany
T. Scholz , Dept. of Design of Integrated Circuits, Tech. Univ. Braunschweig, Germany
pp. 181

A three dimensional register file for superscalar processors (PDF)

K. Shin , Sun Microsyst. Inc., Mountain View, CA, USA
B. Joy , Sun Microsyst. Inc., Mountain View, CA, USA
M. Tremblay , Sun Microsyst. Inc., Mountain View, CA, USA
pp. 191

Reducing memory latency using a small software driven array cache (PDF)

Siu-Chung Lau , Dept. of Comput. Sci., Chinese Univ. of Hong Kong, Shatin, Hong Kong
Chi-Sum Ho , Dept. of Comput. Sci., Chinese Univ. of Hong Kong, Shatin, Hong Kong
Chi-Hung Chi , Dept. of Comput. Sci., Chinese Univ. of Hong Kong, Shatin, Hong Kong
pp. 202

A study of the effects of compiler-controlled speculation on instruction and data caches (PDF)

R.A. Bringmann , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
S.A. Mahlke , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
W.-M.W. Hwu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 211

Commercializing profile-driven optimization (PDF)

J.S. Cox , Database & Compiler Technol., AT&T Global Inf. Solutions, Columbia, SC, USA
D.P. Howell , Database & Compiler Technol., AT&T Global Inf. Solutions, Columbia, SC, USA
T.M. Conte , Database & Compiler Technol., AT&T Global Inf. Solutions, Columbia, SC, USA
pp. 221

A comparative evaluation of software techniques to hide memory latency (PDF)

L.K. John , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
L.D. Coraor , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
V. Reddy , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
P.T. Hulina , Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 229
Scalable Shared-Memory Architectures

Introduction (PDF)

pp. 240

Using hints to reduce the read miss penalty for flat COMA protocols (PDF)

P. Stenstrom , Dept. of Comput. Eng., Lund Univ., Sweden
F. Dahlgren , Dept. of Comput. Eng., Lund Univ., Sweden
M. Bjorkman , Dept. of Comput. Eng., Lund Univ., Sweden
pp. 242

Decoupled pre-fetching for distributed shared memory (PDF)

I. Watson , Dept. of Comput. Sci., Manchester Univ., UK
A. Rawsthorne , Dept. of Comput. Sci., Manchester Univ., UK
pp. 252

Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors (PDF)

A.E. Eichenberger , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
S.G. Abraham , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 262

A survey of software solutions for maintenance of cache consistency in shared memory multiprocessors (PDF)

V. Milutinovic , Sch. of Electr. Eng., Belgrade Univ., Serbia
I. Tartalja , Sch. of Electr. Eng., Belgrade Univ., Serbia
pp. 272
Low Energy ILP Processors

Introduction (PDF)

pp. 284

Energy efficient CMOS microprocessor design (PDF)

T.D. Burd , California Univ., Berkeley, CA, USA
R.W. Brodersen , California Univ., Berkeley, CA, USA
pp. 288

Energy-efficient instruction set architecture for CMOS microprocessors (PDF)

J. Bunda , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D. Fussell , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
W.C. Athas , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 298

Cache designs for energy efficiency (PDF)

A.M. Despain , Adv. Comput. Archit. Lab., Univ. of Southern California, Los Angeles, CA, USA
Ching-Long Su , Adv. Comput. Archit. Lab., Univ. of Southern California, Los Angeles, CA, USA
pp. 306

Power-efficient delay-insensitive codes for data transmission (PDF)

D.S. Fussell , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
P. Patra , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 316

A technique to determine power-efficient, high-performance superscalar processors (PDF)

S.W. Sathaye , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
T.M. Conte , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
K.N.P. Menezes , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
pp. 324

Author Index (PDF)

pp. 354
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