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28th Hawaii International Conference on System Sciences (HICSS'95) (1995)
Hawaii, USA
Jan. 4, 1995 to Jan. 7, 1995
ISSN: 1060-3425
ISBN: 0-8186-6930-6
pp: 95
M. Natale , Encore Comput. Corp., Fort Lauderdale, FL, USA
M. Baker , Encore Comput. Corp., Fort Lauderdale, FL, USA
R. Collins , Encore Comput. Corp., Fort Lauderdale, FL, USA
D. Wilson , Encore Comput. Corp., Fort Lauderdale, FL, USA
S. Lucci , Encore Comput. Corp., Fort Lauderdale, FL, USA
I. Gertner , Encore Comput. Corp., Fort Lauderdale, FL, USA
ABSTRACT
The paper describes a multi-Pentium architecture with a hierarchical memory and an I/O bus subsystem. On a board-level, this architecture achieves a very high-level of integration, by accommodating 8 Pentium processors with up to 2 Gigabytes of RAM. This hierarchical architecture has been extended to support multiple boards in a single cabinet as well as multiple cabinets connected via reflective memory.
INDEX TERMS
parallel architectures; shared memory systems; random-access storage; transaction processing; Pentium MPP; OLTP applications; multi-Pentium architecture; hierarchical memory; I/O bus subsystem; Pentium processors; RAM; hierarchical architecture; multiple boards; multiple cabinets; reflective memory; massively parallel processing
CITATION

M. Natale, M. Baker, D. Wilson, I. Gertner, S. Lucci and R. Collins, "Pentium MPP for OLTP applications," 28th Hawaii International Conference on System Sciences(HICSS), Hawaii, USA, 1995, pp. 95.
doi:10.1109/HICSS.1995.375405
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