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Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track (1989)
Kailua-Kona, HI, USA
Jan. 3, 1989 to Jan. 6, 1989
ISBN: 0-8186-1911-2
TABLE OF CONTENTS

Rapid turn-around design style and technology: impact on computer architecture (PDF)

V.G. Oklobdzija , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 1 vol.1

Emerging design style: how does it impact the way we design? (PDF)

R. Ashany , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 2-4

Rapid architecture prototyper (RAP) (PDF)

M. Andrews , Space Tech Corp., Fort Collins, CO, USA
pp. 5-13

A new method for two dimensional symbolic compaction of IC layout (PDF)

Y. Cheng , Sch. of Electr. Eng., Purdue Univ., W. Lafayette, IN, USA
R. Fujii , Sch. of Electr. Eng., Purdue Univ., W. Lafayette, IN, USA
pp. 14-18

SPARC implementations: ASIC vs. custom design (PDF)

M. Namjoo , Sun Microsyst. Inc., Mountain View, CA, USA
pp. 19-22

A methodology for quick turn-around of high performance DSP ASICS (PDF)

P.H. Ang , LSI Logic Corp., Menlo Park, CA, USA
P.A. Ruetz , LSI Logic Corp., Menlo Park, CA, USA
pp. 23-28

Towards a consistent view of the design tools and process in distributed problem solving environment (PDF)

N. Vidovic , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
D.P. Siewiorek , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
D.F. Vrsalovic , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
Z. Segall , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 29-38

An integrated CAD environment for system design (PDF)

J.M. Pendleton , RISC Int. Syst. Corp., San Jose, CA, USA
C. Burns , RISC Int. Syst. Corp., San Jose, CA, USA
pp. 39-48

BOLD: The Boulder Optimal Logic Design system (PDF)

G. Hachtel , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
M. Lightner , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
K. Bartlett , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
D. Bostwick , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
R. Jacoby , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
P. Moceyunas , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
C. Morrison , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
X. Du , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
E. Schwarz , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 59-73

An integrated CAD system for algorithm-specific IC design (PDF)

C.S. Shung , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R. Jain , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
K. Rimey , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
E. Wang , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
M.B. Srivastava , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
E. Lettang , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
S.K. Azim , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
P.N. Hilfinger , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
J. Rabaey , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.W. Brodersen , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 82-91

Symbolic layout for rapid full-custom prototyping of high-speed telecommunications chips (PDF)

D.G. Boyer , Bellcore, Red Bank, NJ, USA
R.R. Cordell , Bellcore, Red Bank, NJ, USA
pp. 92-101

A rapid turn-around system for designing efficient fine grained signal processors (PDF)

J.A. Beekman , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 102-110

Design management in a workstation environment (PDF)

D. Cooke , Sun Microsyst. Inc., Mountain View, CA, USA
G. Swan , Sun Microsyst. Inc., Mountain View, CA, USA
J. Sirott , Sun Microsyst. Inc., Mountain View, CA, USA
R. Kane , Sun Microsyst. Inc., Mountain View, CA, USA
P. Stevens , Sun Microsyst. Inc., Mountain View, CA, USA
J. Yang , Sun Microsyst. Inc., Mountain View, CA, USA
D. Chen , Sun Microsyst. Inc., Mountain View, CA, USA
pp. 111-117

Real-time computing-tri-dimensional computing (PDF)

B. Furht , MODCOMP R&D Center, Fort Lauderdale, FL, USA
pp. 118-119

A floating communication processor architecture in a distributed real-time system (PDF)

K.G. Shin , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Y. Muthuswamy , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 120-126

G-32-a high performance VSLI 3-D computer (PDF)

L. Carr , MODCOMP/AEG, Fort Lauderdale, FL, USA
R. Kibler , MODCOMP/AEG, Fort Lauderdale, FL, USA
S. Hippen , MODCOMP/AEG, Fort Lauderdale, FL, USA
T. Gargrave , MODCOMP/AEG, Fort Lauderdale, FL, USA
pp. 127-134

Register window management for a real-time multitasking RISC (PDF)

D.J. Quammen , Dept. of Comput. Sci., George Mason Univ., Fairfax, VA, USA
pp. 135-142

Fault-tolerant real-time task scheduling in the MAFT distributed system (PDF)

R.M. Kieckhafer , Dept. of Comput. Sci. & Eng., Nebraska Univ., Lincoln, NE, USA
pp. 143-151

Time complexity modeling and comparison of parallel architectures for Fourier transform oriented algorithms (PDF)

C. Gimarc , Sch. of Electr. Eng., Purdue Univ., W. Lafayette, IN, USA
V. Milutinovic , Sch. of Electr. Eng., Purdue Univ., W. Lafayette, IN, USA
O. Ersoy , Sch. of Electr. Eng., Purdue Univ., W. Lafayette, IN, USA
pp. 160-170

MPC-multiprocessor C language for consistent abstract shared data type paradigms (PDF)

D. Vrsalovic , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
Z. Segall , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
D. Seiwiorek , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
F. Gregoretti , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
E. Caplan , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
C. Fineman , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
S. Kravitz , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
T. Lehr , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
M. Russinovitch , Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, USA
pp. 171-180

A dedicated data flow architecture for hardware compilation (PDF)

M.M. Naini , Dept. of Electr. & Comput. Eng., Florida Atlantic Univ., Boca Raton, FL, USA
pp. 181-190

Hardware support to operations of relational algebra (PDF)

D.M. Velasevic , Dept. of Comput. Sci., Belgrade Univ., Yugoslavia
M.M. Bojovic , Dept. of Comput. Sci., Belgrade Univ., Yugoslavia
pp. 191-200

The Cydra 5 Departmental Supercomputer: design philosophies, decisions and trade-offs (PDF)

B.R. Rau , Cydrome Inc., Milpitas, CA, USA
D.W.L. Yen , Cydrome Inc., Milpitas, CA, USA
W. Yen , Cydrome Inc., Milpitas, CA, USA
R.A. Towle , Cydrome Inc., Milpitas, CA, USA
pp. 202-213

Engineering design of the CONVEX C2 (PDF)

T. Jones , CONVEX Comput. Corp., Richardson, TX, USA
pp. 214-222

Design of the Titan graphics supercomputer (PDF)

G. Miranker , Ardent Comput. Corp., Sunnyvale, CA, USA
J. Rubinstein , Ardent Comput. Corp., Sunnyvale, CA, USA
J. Sanguinetti , Ardent Comput. Corp., Sunnyvale, CA, USA
pp. 223-229

NS32532: case study in general-purpose microprocessor design tradeoffs (PDF)

B. Maytal , Nat. Semicond. Corp., Santa Clara, CA, USA
S. Iacobovici , Nat. Semicond. Corp., Santa Clara, CA, USA
D. Alpert , Nat. Semicond. Corp., Santa Clara, CA, USA
D. Biran , Nat. Semicond. Corp., Santa Clara, CA, USA
J. Levy , Nat. Semicond. Corp., Santa Clara, CA, USA
Y. Sidi , Nat. Semicond. Corp., Santa Clara, CA, USA
pp. 230-241

HP Precision: a spectrum architecture (PDF)

R.B. Lee , Hewlett-Packard, Cupertino, CA, USA
pp. 242-251

High-performance architectures (PDF)

B. Appelbe , Sch. of Inf. & Comput. Sci., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 252-254

Performance measurement of a shared-memory multiprocessor using hardware instrumentation (PDF)

A. Mink , Nat. Inst. of Stand. & Technol., Gaithersburg, MD, USA
G. Nacht , Nat. Inst. of Stand. & Technol., Gaithersburg, MD, USA
pp. 267-276

Improving cache performance by selective cache bypass (PDF)

C.-H. Chi , Philips Lab., Briarcliff Manor, NY, USA
pp. 277-285

Application-transparent process-level error recovery for multicomputers (PDF)

Y. Tamir , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
T.M. Frazier , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 296-305

Cedar architecture and its software (PDF)

P.A. Emrath , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
D.A. Padua , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
P.-C. Yew , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
pp. 306-315

New generation architectures (PDF)

L.G. Friedman , Res. & Dev. Div., NCR Corp., Dayton, OH, USA
pp. 316-318

The design of processing elements on a multiprocessor system with a high-bandwidth, high-latency interconnection network (PDF)

R. Kenner , Courant Inst. of Math. Sci., New York Univ., NY, USA
S. Dickey , Courant Inst. of Math. Sci., New York Univ., NY, USA
P.J. Teller , Courant Inst. of Math. Sci., New York Univ., NY, USA
pp. 319-328

Extended ASLM-a reconfigurable database machine (PDF)

A.R. Hurson , Comput. Eng. Program, Pennsylvania State Univ., University Park, PA, USA
pp. 329-337

A massive memory supercomputer (PDF)

J. Rosenberg , Dept. of Comput. Sci., Newcastle Univ., NSW, Australia
D.M. Koch , Dept. of Comput. Sci., Newcastle Univ., NSW, Australia
J.L. Keedy , Dept. of Comput. Sci., Newcastle Univ., NSW, Australia
pp. 338-345

A system design for real-time fault-tolerant computer networks (PDF)

F.-H.W. Shih , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 346-354

Experiments with a virtual tree machine using transputers (PDF)

D.L. McBurney , Sch. of Inf. Syst., East Anglia Univ., Norwich, UK
M.R. Sleep , Sch. of Inf. Syst., East Anglia Univ., Norwich, UK
pp. 355-364

Reconfigurable transputer processor architectures (PDF)

D.A. Nicole , Dept. of Electron. & Comput. Sci., Southampton Univ., UK
pp. 365-374

Tailoring functional units and memory in a high performance Prolog architecture (PDF)

A. Singhal , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
pp. 375-384

Instruction set architecture of an efficient pipelined dataflow architecture (PDF)

G.R. Gao , Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
pp. 385-392

Extending a Prolog architecture for high performance numeric computations (PDF)

R. Yung , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A.M. Despain , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Y.N. Patt , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 393-402

A top-down parsing co-processor for compilation (PDF)

Y. Chu , Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
pp. 403-413

Interconnection and systems components for digital optics (PDF)

A. Lohmann , Phys. Inst., Erlangen-Nurnberg Univ., West Germany
F. Sauer , Phys. Inst., Erlangen-Nurnberg Univ., West Germany
N. Streibl , Phys. Inst., Erlangen-Nurnberg Univ., West Germany
R. Volkel , Phys. Inst., Erlangen-Nurnberg Univ., West Germany
pp. 424-431

An optical learning machine (PDF)

N.H. Farhat , Dept. of Electr. Eng., Pennsylvania Univ., Philadelphia, PA, USA
Z.-Y. Shae , Dept. of Electr. Eng., Pennsylvania Univ., Philadelphia, PA, USA
pp. 432-439

Diffractive optical elements (PDF)

N.C. Gallagher , Sch. of Electr. Eng., Purdue Univ., W. Lafayette, IN, USA
pp. 440-444

A coherent system for performing an optical transform (PDF)

Guo-Zhen Yang , Inst. of Phys., Acad. Sinica, Beijing, China
Yan-Song Chen , Inst. of Phys., Acad. Sinica, Beijing, China
Shi-Hai Zhing , Inst. of Phys., Acad. Sinica, Beijing, China
Bi-Zhen Dong , Inst. of Phys., Acad. Sinica, Beijing, China
De-Hua Li , Inst. of Phys., Acad. Sinica, Beijing, China
pp. 445-449

Optical modules for future signal processing systems (PDF)

J.N. Lee , US Naval Res. Lab., Washington, DC, USA
pp. 450-459

Space-variant optical parallel logic gate technique and its application to cellular logic architectures (PDF)

T. Yatagai , Inst. of Appl. Phys., Tsukuba Univ., Ibaraki, Japan
Y. Suzaki , Inst. of Appl. Phys., Tsukuba Univ., Ibaraki, Japan
pp. 460-468

Approaches to optical microprogramming (PDF)

R. Forchheimer , Dept. of Electr. Eng., Linkoping Univ., Sweden
pp. 469-472
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