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Proceedings of the Twenty-First Annual Hawaii International Conference on System Sciences. Volume I: Architecture Track (1988)
Kailua-Kona, HI, USA
Jan. 5, 1988 to Jan. 8, 1988
ISBN: 0-8186-0841-2
TABLE OF CONTENTS

High computation performance through efficient access of data structures (PDF)

P.T. Hulina , Dept. of Electr. Eng., Pennsylvania State Univ., PA, USA
L.D. Coraor , Dept. of Electr. Eng., Pennsylvania State Univ., PA, USA
O.A. Morean , Dept. of Electr. Eng., Pennsylvania State Univ., PA, USA
pp. 4-9

Back end architecture based on transformed inverted lists-A surrogate file structure for a very large data/knowledge base (PDF)

N.I. Hachem , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
P.B. Berra , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 10-19

MUTABOR-A coprocessor supporting object-oriented memory management and error recovery (PDF)

J. Kaiser , Gesellschaft fur Math. und Datenverarbeitung mbH, St. Augustin, West Germany
E. Nett , Gesellschaft fur Math. und Datenverarbeitung mbH, St. Augustin, West Germany
R. Kroger , Gesellschaft fur Math. und Datenverarbeitung mbH, St. Augustin, West Germany
pp. 20-29

HPSm2: A refined single-chip microengine (PDF)

W.W. Hwu , Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 30-40

A VLSI join module (PDF)

A.R. Hurson , Dept. of Electr. Eng., Pennsylvania State Univ., University Park, PA, USA
C.R. Petrie , Dept. of Electr. Eng., Pennsylvania State Univ., University Park, PA, USA
J.B. Cheng , Dept. of Electr. Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 41-49

An exercise in high level language architecture design (PDF)

M.J. Thazhuthaveetil , Dept. of Electr. Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 50-58

Multiple-bus multiprocessor systems (PDF)

D.J. Pease , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 59-69

A multi-transputer architecture for parallel logic programs (PDF)

P. Biswas , Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
S.-C. Su , Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
D. Wright , Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
pp. 70-79

The DSI and below: The architelcture/hardware component of a computer science curriculum (PDF)

Y.N. Patt , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
pp. 81-84

Teaching computer architecture as engineering design with VLSI (PDF)

S.P. Levitan , Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
J.T. Cain , Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
pp. 85-90

Logic design education at Stanford University (PDF)

J.F. Wakerly , Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
E.J. McCluskey , Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
pp. 91-98

Computer architecture education: An integrated classroom and laboratory experience (PDF)

M.C. Mulder , Dept. of Electr. Eng., Portland Univ., OR, USA
O.G. Samman , Dept. of Electr. Eng., Portland Univ., OR, USA
pp. 99-105

Computer science accreditation-real needs, real concerns, real progress (PDF)

S.H. Zweben , Dept. of Comput. & Inf. Sci., Ohio State Univ., Columbus, OH, USA
pp. 106-110

Mapping parallel algorithms onto general-purpose parallel machines (PDF)

M.C. Chen , Dept. of Comput. Sci., Yale Univ., New Haven, CT, USA
pp. 131-141

SVD computation on the Connection Machine (PDF)

L.M. Ewerbring , Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
F.T. Luk , Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
pp. 142-147

A matching approach to utilizing fine-grained parallelism (PDF)

R. Gupta , Philips Labs., Briarcliff Manor, NY, USA
pp. 148-156

A dynamic-trace-driven simulator for evaluating parallelism (PDF)

I. Mathieson , Dept. of Comput. Sci., La Trobe Univ., Bundoora, Vic., Australia
R. Francis , Dept. of Comput. Sci., La Trobe Univ., Bundoora, Vic., Australia
pp. 158-166

The effect of application characteristics on performance in a parallel architecture (PDF)

A. Guzman , Adv. Comput. Archit. Program, MCC, Austin, TX, USA
E.J. Krall , Adv. Comput. Archit. Program, MCC, Austin, TX, USA
P.F. McGehearty , Adv. Comput. Archit. Program, MCC, Austin, TX, USA
N. Bagherzadeh , Adv. Comput. Archit. Program, MCC, Austin, TX, USA
pp. 167-173

Reliability of the shuffle-exchange network and its variants (PDF)

J.T. Blake , Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
K.S. Trivedi , Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
pp. 174-182

TLB consistency on highly-parallel shared-memory multiprocessors (PDF)

P.J. Teller , Courant Inst. of Math. Sci., New York Univ., NY, USA
R. Kenner , Courant Inst. of Math. Sci., New York Univ., NY, USA
pp. 184-193

Hardware support for efficient execution of Ada tasking (PDF)

A. Ardo , Dept. of Comput, Eng., Lund Univ., Sweden
pp. 194-202

Mesh-connected array processors with bypass capability for signal/image processing (PDF)

D. Kim , Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
K. Hwang , Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 203-210

VLSI support for a cactus stack oriented memory organization (PDF)

P. Stenstrom , Dept. of Comput. Eng., Lund Univ., Sweden
pp. 211-220

Architecture for single-chip ASIC processor with integrated floating point unit (PDF)

V.G. Oklobdzija , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 221-229

A RISC architecture for multitasking (PDF)

D. Quammen , George Mason Univ., Fairfax, VA, USA
D.K. DuBose , George Mason Univ., Fairfax, VA, USA
D. Tabak , George Mason Univ., Fairfax, VA, USA
pp. 230-237

Organization, management and VLSI implementation of a multiple register window file for LISP-oriented architectures (PDF)

B. Furht , Dept. of Electr. & Comput. Eng., Miami Univ., Coral Gables, FL, USA
H.A. Aboalsamh , Dept. of Electr. & Comput. Eng., Miami Univ., Coral Gables, FL, USA
W.H. Chia , Dept. of Electr. & Comput. Eng., Miami Univ., Coral Gables, FL, USA
Y.N. Lai , Dept. of Electr. & Comput. Eng., Miami Univ., Coral Gables, FL, USA
pp. 238-247

Process graph analyzer: a front end tool for VHDL behavioral synthesis (PDF)

J. Bhasker , Honeywell Corp. Syst. Dev. Div., Golden Valley, NM, USA
pp. 248-255

A compiler-writer's view of GaAs computer system design (PDF)

H. Dietz , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
C.-H. Chi , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 256-265

Register allocation for GaAs computer systems (PDF)

C.-H. Chi , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
H.G. Dietz , Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 266-274

Modelling and analysis of stochastic propagation delays in GaAs adders (PDF)

B. Perunicic , Dept. of Electr. Eng., Illlinois Univ., Urbana, IL, USA
pp. 275-286

A RISC architectural design of the HERMES multiprocessor vision machine (PDF)

N.G. Bourbakis , Sch. of Inf. Technol. & Eng., George Mason Univ., Fairfax, VA, USA
D. Tabak , Sch. of Inf. Technol. & Eng., George Mason Univ., Fairfax, VA, USA
pp. 287-293

Mapping loop algorithms into reconfigurable mesh connected processor array (PDF)

H.Y.H. Chuang , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
L. Chen , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
C.S. Kannan , Dept. of Comput. Sci., Pittsburgh Univ., PA, USA
pp. 294-300

Transformation of numerical algorithms for data-flow processing (PDF)

J.L. Gaudiot , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Y.H. Wei , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 301-310

Fault tolerance in linear systolic arrays using time redundancy (PDF)

A. Majumdar , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
C.S. Raghavendra , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
M.A. Breuer , Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 311-320
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