2011 IEEE 13th International Symposium on High-Assurance Systems Engineering (2011)
Boca Raton, Florida USA
Nov. 10, 2011 to Nov. 12, 2011
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/HASE.2011.33
The current trend in the silicon industry has been a steady migration towards Chip Multicore Processor (CMP) system to harvest more throughputs. However, chip multicore processors report higher values of soft errors, thereby degrading the overall system reliability. Hence, engineers have been wary of using CMP architectures for safety-critical embedded real-time system applications that require high reliability levels. The larger users of these processors also dictate the processor migration trends. With newer processor architectures, the older ones are destined to become obsolete. This paper compares typical safety-critical architectures and investigates the reliabilities of different CMP architectures. We present the fault tolerance framework and detailed reliability analysis of fault-tolerant single-core and multi-core based systems. The analysis results are then used to compare the reliability of CMP architectures with the corresponding reliability of single processor architectures. Although a CMP system does encounter degradation, by applying some system level dependability assurance mitigation features, its reliability can be enhanced. This enables CMP systems to be effectively deployed in critical applications.
Reconfigurable Chip Multicore Processors (CMP), Multicore, Reliabiltiy, Soft Errors, Transient faults, Markov model
F. B. Bastani, I. Yen and M. Peshave, "High-Assurance Reconfigurable Multicore Processor Based Systems," 2011 IEEE 13th International Symposium on High-Assurance Systems Engineering(HASE), Boca Raton, Florida USA, 2011, pp. 220-226.