The Community for Technology Leaders
Great Lakes Symposium on VLSI (1999)
Ann Arbor, Michigan
Mar. 4, 1999 to Mar. 6, 1999
ISSN: 1066-1395
ISBN: 0-7695-0104-4
TABLE OF CONTENTS
Session 1: Plenary Session-Invited Papers

MEMs (PDF)

pp. 0
Session 2A: Testing

PASTA: Partial Scan to Enhance Test Compaction (Abstract)

Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , University of Iowa
pp. 4

On Applying Set Covering Models to Test Set Compaction (Abstract)

João P. Marques-Silva , Cadence European Labs/INESC
Horácio C. Neto , Cadence European Labs/INESC
Paulo F. Flores , Cadence European Labs/INESC
pp. 8

On Test Generation with A Limited Number of Tests (Abstract)

Kozo Kinoshita , Osaka University
Hideyuki Ichihara , Osaka University
Seiji Kajihara , Osaka University and Kyushu Institute of Technology
pp. 12

Functional ATPG for Delay Faults (Abstract)

M. Michael , The University of Arizona
S. Tragoudas , The University of Arizona
pp. 16

On Path Delay Fault Testing of Multiplexer - Based Shifters (Abstract)

Y. Tsiatouhas , ISD S.A
H.T. Vergos , University of Patras and Computer Technology Institute
D. Nikolos , University of Patras and Computer Technology Institute
Th. Haniotakis , ISD S.A
pp. 20

A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation (Abstract)

C. Landrault , Universit? Montpellier II / CNRS
S. Pravossoudovitch , Universit? Montpellier II / CNRS
L. Guiller , Universit? Montpellier II / CNRS
P. Girard , Universit? Montpellier II / CNRS
pp. 24
Session 2B: VLSI Design 1

VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing (Abstract)

Aamir A. Farooqui , University of California at Davis
Vojin G. Oklobdzija , University of California at Davis and Integration Berkeley
pp. 30

The Design of a Register Renaming Unit (Abstract)

Thomas P. Kelliher , Pennsylvania State University
Mary Jane Irwin , Pennsylvania State University
Benjamin Bishop , Pennsylvania State University
pp. 34

Efficient and Safe Asynchronous Wave-Pipeline Architectures for Datapath and Control Unit Applications (Abstract)

M. Garg , Darmstadt University of Technology
O. Hauck , Darmstadt University of Technology
S. A. Huss , Darmstadt University of Technology
pp. 38

Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM (Abstract)

Jörg Hilgenstock , Universit?t Hannover
Peter Pirsch , Universit?t Hannover
Klaus Herrmann , Universit?t Hannover
pp. 42

Adaptive Hard Disk Power Management on Personal Computers (Abstract)

Yung-Hsiang Lu , Stanford University
Giovanni de Micheli , Stanford University
pp. 50
Session 3A: Delay Modeling

Inductance Effects in RLC Trees (Abstract)

Yehea I. Ismail , University of Rochester and IBM Microelectronics
Jose L. Neves , University of Rochester and IBM Microelectronics
Eby G. Friedman , University of Rochester and IBM Microelectronics
pp. 56

S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric (Abstract)

Altan Odabasioglu , Carnegie Mellon University
Lawrence T. Pileggi , Carnegie Mellon University
Emrah Acar , Carnegie Mellon University
Mustafa Celik , Carnegie Mellon University
pp. 60
Session 3B: VLSI Design 2

A Radix-16 SRT Division Unit with Speculation of the Quotient Digits (Abstract)

Gianluca Cornetta , Universit?t Polit?cnica de Catalunya
Jordi Cortadella , Universit?t Polit?cnica de Catalunya
pp. 74

Area-Efficient Area Pad Design for High Pin-Count Chips (Abstract)

Louis Luh , University of Southern California
John Choma, Jr. , University of Southern California
Jeffrey Draper , University of Southern California
pp. 78

New 2 Gbit/s CMOS I/O pads (Abstract)

Gianluca Piccinini , Polit?cnico di Torino
Maurizio Zamboni , Polit?cnico di Torino
Massimo Ruo Roth , Polit?cnico di Torino
Guido Masera , Polit?cnico di Torino
pp. 82
Session 4A: Analog and Digital Testing

On Optimizing Test Strategies for Analog Cells (Abstract)

Joan Figueras , Universit?t Polit?cnica de Catalunya
Anna M. Brosa , Universit?t Polit?cnica de Catalunya
pp. 92

Novel Design for Testability of a Mixed-Signal VLSI IC (Abstract)

E. McShane , University of Illinois at Chicago
K. Shenai , University of Illinois at Chicago
V. Boyadzhyan , California Institute of Technology
B. Blaes , California Institute of Technology
W.C. Fang , California Institute of Technology
E. Kolawa , California Institute of Technology
L. Alkalai , California Institute of Technology
pp. 97

The Development of Analog SPICE Behavioral Model Based on IBIS Model (Abstract)

Ying Wang , Nanyang Technological University
Han Ngee Tan , Nanyang Technological University
pp. 101

Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits (Abstract)

Yanging Xu , University of Saskatchewan
Carl McCrosky , University of Saskatchewan
Mostafa Abd-El-Barr , King Fahd University of Petroleum & Minerals
pp. 388

Fault Coverage Estimation for Early Stage of VLSI Design (Abstract)

Tom Chen , Colorado State University
Von-Kyoung Kim , Sun Microsystems
Mick Tegetho , Celestica
pp. 105

Pseudo-Exhaustive Testing of Sequential Circuits (Abstract)

Bassam Shaer , University of Minnesota
Sami A. Al-Arian , University of South Florida
David Landis , Pennsylvania State University
pp. 109
Session 4B: Nanoelectronics 1

Self-Assembly Based Approaches for Metal/Molecule/Semiconductor Nanoelectronic Circuits (Abstract)

J. Liu , Purdue University
B.L. Walsh , Purdue University
V.R. Kolagunta , Purdue University
T. Lee , Purdue University
J.M. Woodall , Purdue University
B. Kasibhatla , University of California at San Diego
C. P. Kubiak , University of California at San Diego
E.L. Peckham , Purdue University
D.B. Janes , Purdue University
J. Lauterbach , Purdue University
R.P. Andres , Purdue University
R. Reifenberger , Purdue University
H.J. Ueng , Purdue University
M.R. Melloch , Purdue University
E.H. Chen , Purdue University
T. Pletcher , Purdue University
J. Dicke , Purdue University
pp. 114

Logic in Wire: Using Quantum Dots to Implement a Microprocessor (Abstract)

Peter M. Kogge , University of Notre Dame
Michael T. Niemier , University of Notre Dame
pp. 118

Why is Time-Varying Control Necessary for Signal Processing with Locally-Connected Quantum-Dot Arrays? (Abstract)

Árpád. I. Csurgay , University of Notre Dame
Craig S. Lent , University of Notre Dame
Wolfgang Porod , University of Notre Dame
pp. 122

Transport in Split Gate MOS Quantum Dot Structures (Abstract)

D.K. Ferry , Arizona State University,
M.J. Rack , Arizona State University,
S.M. Goodnick , Arizona State University,
D. Vasileska-Kafedezka , Arizona State University,
J. Bird , Arizona State University,
M. Kozicki , Arizona State University,
M.D. Khoury , Arizona State University,
T.J. Thornton , Arizona State University,
A.D. Gunther , Arizona State University,
pp. 394

Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the 10-100 GHz Domain (Abstract)

A.C. Seabaugh , Raytheon Systems Company
B. Brar , Raytheon Systems Company
F. Morris , Raytheon Systems Company
G. Frazier , Raytheon Systems Company
T.P.E. Broekaert , Raytheon Systems Company
pp. 123
Session 5A: Synthesis

Reducing BDD Size by Exploiting Structural Connectivity (Abstract)

Ronnie L. Wright , Michigan State University
Michael A. Shanblatt , Michigan State University
pp. 132

An Integrated Approach for Synthesizing LUT Networks (Abstract)

Shigeru Yamashita , NTT Communication Science Laboratories
Akira Nagoya , NTT Communication Science Laboratories
Hiroshi Sawada , NTT Communication Science Laboratories
pp. 136

Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops (Abstract)

Abhijit Ghosh , University of Cincinnati
Ranga Vemuri , University of Cincinnati
Sandeep K. Lodha , University of Cincinnati
pp. 140

Design Issues in Synthesis of Reusable Cores (Abstract)

Rohit Sharma , Texas Instruments Ltd.
C.P. Ravikumar , Indian Institute of Technology
pp. 144
Session 5B: Nanoelectronics 2

Ultrahigh-Speed Circuits Using Resonant Tunneling Devices (Abstract)

T. Itoh , NTT System Electronics Laboratories
H. Matsuzaki , NTT System Electronics Laboratories
M. Yamamoto , NTT System Electronics Laboratories
T. Waho , NTT System Electronics Laboratories
T. Akeyoshi , NTT System Electronics Laboratories
J. Osaka , NTT System Electronics Laboratories
pp. 150

Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit (Abstract)

Tetsuya Uemura , NEC Corporation
Pinaki Mazumder , The University of Michigan
pp. 158

Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit Applications (Abstract)

J. Schulman , HRL Laboratories
W. Williamson , Institute for Defense Analysis
P. Fay , University of Notre Dame
P. Mazumder , University of Michigan
D. Chow , HRL Laboratories
B. Gilbert , Mayo Foundation
G.H. Bernstein , University of Notre Dame
pp. 162

A Memory Design in QCAs using the SQUARES Formalism (Abstract)

D. Berzon , University College London
T.J. Fountain , University College London
pp. 166
Session 6A: Design Issues

Transistor Level Synthesis for Static CMOS Combinational Circuits (Abstract)

Jacob A. Abraham , The University of Texas at Austin
Chia-Pin R. Liu , The University of Texas at Austin
pp. 172

SINMEF - A Decomposition Based Synthesis Tool for Large FSMs (Abstract)

Carlos Humberto Llanos Quintero , Universidade de Brasilia
Marius Strum , Universidade de S?o Paulo
pp. 176

An Approach for Testing Safety-Critical Software (Abstract)

Weiwei Li , Shanghai Tie Dao University
Zhongwei Xu , Shanghai Tie Dao University
Yan Jin , Shanghai Tie Dao University
pp. 180

Design Recovery for Incomplete Combinational Logic (Abstract)

Moon-Jung Chung , Michigan State University
Travis E. Doom , Wright State University
Anthony S. Wojcik , Michigan State University
pp. 184

Regression-Based Macromodeling for Delay Estimation of Behavioral Components (Abstract)

M. Poncino , Universit?t Polit?cnico di Torino
R. Scarsi , Universit?t Polit?cnico di Torino
E. Macii , Universit?t Polit?cnico di Torino
G. Odasso , Universit?t Polit?cnico di Torino
A. Macii , Universit?t Polit?cnico di Torino
pp. 188

Efficiently Searching the Optimal Design Space (Abstract)

Stephen A. Blythe , Saint Louis University
Robert A. Walker , Kent State University
pp. 192
Session 6B: VLSI Circuits 1

A Bandpass Sigma-Delta for Software Low-Power and Low-Voltage Radio by Using PATH Technique (Abstract)

Ward J. Helms , University of Washington
John Ling , University of Washington
Yiu (Simon) Wu , University of Washington
pp. 198

No-Race Charge-Recycling Differential Logic (NCDL) (Abstract)

Sung-Mo (Steve) Kang , University of Illinois at Urbana-Champaign
Seung-Moon Yoo , University of Illinois at Urbana-Champaign
pp. 202

Linear Transconductors Using Low Voltage Low Power Square-Law Cmos Cells (Abstract)

Tuna B. Taram , Istanbul Technical University and Ohio State University
Mohammed Ismail , Ohio State University
pp. 206

Parallel Saturating Fractional Arithmetic Units (Abstract)

Michael Schulte , Lehigh University
Navindra Yadav , Lehigh University
John Glossner , Lucent Technologies, Inc.
pp. 214
Session 6C: Short Papers 1

Modell Evaluation Using Genetic Manipulation Techniques (Abstract)

Z. Stamenkovic , University of Nis
U. Glaeser , The German National Research Center for Information Technology (GMD)
H.-Ch. Dahmen , The German National Research Center for Information Technology (GMD)
pp. 224

A Genetic Algorithm for Register Allocation (Abstract)

K.M. Elleithy , King Fahd University of Petroleum and Minerals
E.G. Abd-El-Fattah , Moshamit Behera Company
pp. 226

Formal Verification of Tree-Structured Carry-Lookahead Adders (Abstract)

Sae Hwan Kim , Syracuse University
Shiu-Kai Chin , Syracuse University
pp. 232

Bounding Algorithms for Design Space Exploration (Abstract)

Robert A. Walker , Kent State University
Samit Chaudhuri , Magrnu Design Automatim
pp. 234

Digital Neural Processing Unit for Electronic Nose (Abstract)

Mahmoud Al-Nsour , Oakland University
Hoda S. Abdel-Aty-Zohdy , Oakland University
pp. 236

A Low Power Charge-Recycling CMOS Clock Buffer (Abstract)

Wolfgang Porod , University of Notre Dame
Xiaohui Wang , University of Notre Dame
pp. 238

A Multiple-Input Single-Phase Clock Flip-Flop Family (Abstract)

Allan R. Dyck , Simon Fraser University
Richard F. Hobson , Simon Fraser University
pp. 240

VHDL Design of a Test Processor Based on Mixed-Mode Test Generation (Abstract)

Zahari Mohamed Darus , Universiti Kebangsaan Malaysia
Md. Altaf-Ul-Amin , Universiti Kebangsaan Malaysia
pp. 244
Session 7A: Physical Design

An Incremental Floorplanner (Abstract)

Majid Sarrafzadeh , Northwestern University
Pradeep Prabhakaran , Compaq-Digital
Prithviraj Banerjee , Northwestern University
Jim Crenshaw , Motorola
pp. 248

A Greedy Router with Technology Targetable Output (Abstract)

R. Balakrishnan , Simon Fraser University
R.F. Hobson , Simon Fraser University
pp. 252

Routability Prediction for Hierarchical FPGAs (Abstract)

Wei Li , Nortel Technologies
D.K. Banerji , University of Guelph
pp. 256
Session 7B: MEMS

Design Automation of MEMS Systems Using Behavioral Modeling (Abstract)

Carla Purdy , University of Cincinnati
Dennis Gibson , University of Cincinnati
Fred Beyette, Jr. , University of Cincinnati
Alva Hare , University of Cincinnati
pp. 266

Numerical Tools for Fracture of MEMS Devices (Abstract)

N. Tayebi , Case Western Reserve University
Y. Belkacemi , Ecole Nationale Polytechnique of Algeria
A.K. Tayebi , Cornell University
pp. 274
Session 8A: Verification

Formal Checking of Properties in Complex Systems Using Abstractions (Abstract)

Jacob A. Abraham , The University of Texas at Austin
Dinos Moundanos , The University of Texas at Austin
pp. 280

Symbolic Multi-Level Verification of Refinement (Abstract)

Luc Claesen , IMEC vzw/Katholieke Universiteit Leuven
Stefan Hendricx , IMEC vzw/Katholieke Universiteit Leuven
pp. 288

Self-Checking of FPGA-Based Control Units (Abstract)

Vladimir Sinelnikov , Tel Aviv University
Ilya Levine , Tel Aviv University
pp. 292

A Software Acceptance Testing Technique Based on Knowledge Accumulation (Abstract)

Fangmei Wu , Shanghai Tiedao University
Yi Yu , Shanghai Tiedao University
pp. 296

A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability (Abstract)

Yong Chang Kim , University of Wisconsin-Madison
Kewal K. Saluja , University of Wisconsin-Madison
Vishwani D. Agrawal , Lucent Technologies
pp. 300
Session 8B: VLSI Circuits 2

A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers (Abstract)

M.I. Elmasry , University of Waterloo
Amr N. Hafez , University of Waterloo
pp. 306

NMOS Energy Recovery Logic (Abstract)

Chulwoo Kim , University of Illinois at Urbana-Champaign
Sung-Mo (Steve) Kang , University of Illinois at Urbana-Champaign
Seung-Moon Yoo , University of Illinois at Urbana-Champaign
pp. 310

Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems (Abstract)

Radu M. Secareanu , University of Rochester
William Staub , University of Rochester
Christopher Morton , University of Rochester
Thomas E. Watrobski , University of Rochester
Ivan S. Kourtev , University of Rochester
Thomas Tellier , University of Rochester
Juan Becerra , University of Rochester
Eby G. Friedman , University of Rochester
pp. 314

An all Digital BiCMOS Phase Lock Loop for VLSI Processors (Abstract)

S.M. Rezaul Hasan , Universiti Sains Malaysia
Lim Chu Aun , Intel Microelectronics
pp. 318

Low Power Techniques for Digital GaAs VLSI (Abstract)

D. Abbott , University of Adelaide
J.F. López , University Las Palmas de Gran Canaria
A. Núñez , University Las Palmas de Gran Canaria
S. Lachowicz , Edith Cowan University
R. Sarrniento , University Las Palmas de Gran Canaria
K. Eshraghian , Edith Cowan University
pp. 321

A VLSI Architecture for ATM Algorithm-Agile Encryption (Abstract)

M.A. Hasan , University of Waterloo
A.G. Wassal , University of Waterloo
pp. 325
Session 8C: Short Papers 2

Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS (Abstract)

E. McShane , University of Illinois at Chicago
K. Shenai , University of Illinois at Chicago
W.C. Fang , California Institute of Technology
V. Boyadzhyan , California Institute of Technology
L. Alkalai , California Institute of Technology
B. Blaes , California Institute of Technology
E. Kolawa , California Institute of Technology
pp. 332

A Fully Pipelined, 700MBytes/s DES Encryption Core (Abstract)

Craig S. Steele , University of Southern California
Ihn Kim , University of Southern California
Jefferey G. Koller , University of Southern California
pp. 386

Proposal of Data-Driven Processor Architecture Qv-K1 (Abstract)

Hiroaki Terada , Kochi University of Technology
Makoto Iwata , Kochi University of Technology
Koso Murakami , Osaka University
Teruhiko Kamigata , Osaka University
pp. 336

Accurate Resource Estimation Algorithms for Behavioral Synthesis (Abstract)

Srinivas Katkoori , University of South Florida
Ranga Vemuri , University of Cincinnati
pp. 338

Assessing Defect Coverage of Memory Testing Algorithms (Abstract)

Vonkyoung Kim , Sun Microsystems
Tom Chen , Colorado State University
pp. 340

Memory Chip BIST Architecture (Abstract)

Jacob Savir , New Jersey Institute of Technology
pp. 384

Exploiting Test Resource Optimization in Data Path Synthesis for BIST (Abstract)

Paul Y.S. Cheung , University of Hong Kong
Xiaowei Li , Peking University
pp. 342

Resonant Tunneling Transistors for Threshold Logic Circuit Applications (Abstract)

W. Prost , Universit?t Duisburg
U. Auer , Universit?t Duisburg
P. Glösekötter , Universit?t Dortmund
C. Pacha , Universit?t Dortmund
F.-J. Tegude , Universit?t Duisburg
K. Goser , Universit?t Dortmund
pp. 344
Session 9A: Low Power

ALPS: A Peak Power Estimation Tool for Sequential Circuits (Abstract)

M. Rebaudengo , Polit?cnico di Torino
M. Sonza Reorda , Polit?cnico di Torino
F. Corno , Polit?cnico di Torino
M. Violante , Polit?cnico di Torino
pp. 350

Clustered Table-Based Macromodels for RTL Power Estimation (Abstract)

Roberto Corgnati , Universit?t Polit?cnico di Torino
Enrico Macii , Universit?t Polit?cnico di Torino
Massimo Poncino , Universit?t Polit?cnico di Torino
pp. 354

The Design of Cmos Gigahertz-Band Continuous-Time Active Lowpass Filters with Q-Enhancement Circuits (Abstract)

John Choma, Jr. , University of Southern California
Yuyu Chang , University of Southern California
Jack Wills , University of Southern California
pp. 358

A New Algorithm for RNS Magnitude Comparison Based on New Chinese Remainder Theorem II (Abstract)

Yuke Wang , Concordia University
Mostapha Aboulhamid , Universite de Montreal
Xiaoyu Song , Universite de Montreal
pp. 362
Session 9B: VLSI Circuits 3

Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method (Abstract)

Makoto Ikeda , University of Tokyo
Kunihiro Asada , University of Tokyo
Satoshi Komatsu , University of Tokyo
pp. 368

A 1.8V High Dynamic-Range CMOS High-Speed Four Quadrant Multiplier (Abstract)

Mohammed Ismail , Ohio State University
Chi-Hung Lin , Ohio State University
pp. 372

A Novel Low Power Energy Recovery Full Adder Cell (Abstract)

L.K. John , University of Texas at Austin
E. John , University of Texas - Pan American
R. Shalem , University of Texas at Austin
pp. 380

Author Index (PDF)

pp. 397
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