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Great Lakes Symposium on VLSI (1998)
Lafayette, Louisiana
Feb. 19, 1998 to Feb. 24, 1998
ISSN: 1066-1395
ISBN: 0-8186-8409-7
TABLE OF CONTENTS

Foreword (PDF)

pp. viii
Low Power Circuits and Architectures

Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding (Abstract)

Luca Benini , Stanford University
Enrico Macii , Politecnico di Torino
Alberto Macii , Politecnico di Torino
Giovanni de Micheli , Stanford University
Massimo Poncino , Politecnico di Torino
pp. 8

A Low-Power High-Performance Embedded SRAM Macrocell (Abstract)

M.I. Elmasry , University of Waterloo
A.M. Fahim , University of Waterloo
M. Khellah , University of Waterloo
pp. 13

Low-Power Design of Finite Field Multipliers for Wireless Applications (Abstract)

A.G. Wassal , University of Waterloo
M.I. Elmasry , University of Waterloo
M.A. Hasan , University of Waterloo
pp. 19

Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines (Abstract)

Jose L. Neves , IBM Microelectronics
Yehea I. Ismail , University of Rochester
Eby G. Friedman , University of Rochester
pp. 39
VLSI Circuits

A VLSI High-Performance Encoder with Priority Lookahead (Abstract)

Jabulani Nyathi , State University of New York, Binghamton
Jose G. Delgado-Frias , State University of New York, Binghamton
pp. 59

Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes (Abstract)

Pinaki Mazumder , The University of Michigan, Ann Arbor
Mayukh Bhattacharya , The University of Michigan, Ann Arbor
pp. 65

600 MHz Digitally Controlled BiCMOS Oscillator (DCO) for VLSI Signal Processing & Communication Applications (Abstract)

Azman M. Yusof , Universiti Sains Malaysia
Lim Chu Aun , Universiti Sains Malaysia
S.M. Rezaul Hasan , Universiti Sains Malaysia
pp. 71

Stability of a Continuous-Time State Variable Filter with OP-AMP and OTA-C Integrators (Abstract)

John Choma, Jr. , Univeristy of Southern California
Tim Bakken , Univeristy of Southern California
pp. 77

Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic (Abstract)

T. Stouraitis , University of Patras
A. Thanailakis , Democritus University of Thrace
I. Karafyllidis , Democritus University of Thrace
D. Soudris , Democritus University of Thrace
I. Thoidis , Democritus University of Thrace
pp. 83

Design of Clock Distribution Networks in Presence of Process Variations (Abstract)

M. Nekili , Ecole Polytechnique of Montreal
Y. Savaria , Ecole Polytechnique of Montreal
G. Bois , Ecole Polytechnique of Montreal
pp. 95

A Novel 1.5-V Cmos Mixer (Abstract)

G. Palmisano , UNIVERSITA' DI CATANIA
G. Palumbo , UNIVERSITA' DI CATANIA
C. Strano , UNIVERSITA' DI CATANIA
G. Giustolisi , UNIVERSITA' DI CATANIA
pp. 113
VLSI Architectures

A VLSI Self-Compacting Buffer for DAMQ Communication Switches (Abstract)

Richard Diaz , State University of New York, Binghamton
Jose G. Delgado-Frias , State University of New York, Binghamton
pp. 128

A Dictionary Machine Emulation on a VLSI Computing Tree System (Abstract)

Adger E. Harvin, III , State University of New York, Binghamton
Jose G. Delgado-Frias , State University of New York, Binghamton
pp. 134

Modeling and Analysis of The Difference-Bit Cache (Abstract)

Soumya Pillai , The University of Texas at Austin
Ashutosh Kulkarni , The University of Texas at Austin
Navin Chander , The University of Texas at Austin
Lizy John , The University of Texas at Austin
pp. 140

Modeling of Shift Register-based ATM Switch (Abstract)

Sandeep Agarwal , University of Victoria
Fayez El-Guibaly , University of Victoria
pp. 146

An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement (Abstract)

Jen-Chien Tuan , National Chiao-Tung University
Chein-Wei Jen , National Chiao-Tung University
pp. 152

Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning (Abstract)

Qutaibah Malluhi , Jackson State University
Bassem A. Alhalabi , Florida Atlantic University
Rafic Ayoubi , University of Balamand
pp. 168
VLSI Arithmetic

Residue to Binary Number Converters for (2^n-1, 2^n, 2^n+1) (Abstract)

Yuke Wang , Concordia University
Xiaoyu Song , Universite de Montreal
Mostapha Aboulhamid , Universite de Montreal
pp. 174

The Design of Residue Number System Arithmetic Units for A VLSI Adaptive Equalizer (Abstract)

Inseop Lee , University of Illinois at Urbana-Champaign
W. Kenneth Jenkins , University of Illinois at Urbana-Champaign
pp. 179

Merged Arithmetic for Computing Wavelet Transforms (Abstract)

Gwangwoo Choe , The University of Texas at Austin
Earl E. Swartzlander, Jr. , The University of Texas at Austin
pp. 196

Digital Arithmetic Using Analog Arrays (Abstract)

Saeid Sadeghi-Emamchaie , University of Windsor
V. Dimitrov , University of Windsor
G.A. Jullien , University of Windsor
W.C. Miller , University of Windsor
pp. 202

A Combined Interval and Floating Point Multiplier (Abstract)

James E. Stine , Lehigh University
Michael J. Schulte , Lehigh University
pp. 208
Testing

A Unified Approach for a Time-Domain Built-In Self-Test Technique and Fault Detection (Abstract)

B. Provost , Texas A&M University
E. Sánchez-Sinencio , Texas A&M University
A.M. Brosa , Universitat Polit?cnica de Catalunya
pp. 230
VLSI Communication Circuits and Systems

Design Issues of LC Tuned Oscillators for Integrated Transceivers (Abstract)

A. Zanchi , Politecnico di Milano
A.L. Lacaita , Politecnico di Milano
C. Samori , Politecnico di Milano
P. Vita , SGS-Thomson Microelectronics
pp. 264

Novel Simple Models Of Cml Propagation Delay (Abstract)

G. Palumbo , UNIVERSITA' DI CATANIA
M. Alioto , UNIVERSITA' DI CATANIA
pp. 270

Low Voltage Low power CMOS AGC circuit for wireless communication (Abstract)

Hassan O. Elwan , Ohio State University
Mohammed Ismail , Ohio State University
pp. 281

A Continuous-Time Switched-Current $\Sigma\Delta$ Modulator with Reduced Loop Delay (Abstract)

Louis Luh , University of Southern California
John Choma, Jr. , University of Southern California
Jeffrey Draper , University of Southern California
pp. 286
Algorithms

An Exact Input Encoding Algorithm for BDDs Representing FSMs (Abstract)

Alexander Saldanha , Cadence Berkeley Laboratories
Wilsin Gosti , University of California Berkeley
Tiziano Villa , PARADES
Alberto L. Sangiovanni-Vincentelli , University of California Berkeley
pp. 294

Maximum Current Estimation in Programmable Logic Arrays (Abstract)

I.N. Hajj , University of Illinois at Urbana-Champaign
S. Bobba , University of Illinois at Urbana-Champaign
pp. 301

Identifying High-Level Components in Combinational Circuits (Abstract)

Travis Doom , Michigan State University
Greg Chisholm , Argonne National Laboratory
Jennifer White , Michigan State University
Anthony S. Wojcik , Michigan State University
pp. 313

Linear Transformations and Exact Minimization of BDDs (Abstract)

Wolfgang Günther , Albert-Ludwigs-University
Rolf Drechsler , Albert-Ludwigs-University
pp. 325

Timed Supersetting and the Synthesis of Telescopic Units (Abstract)

Luca Benini , Stanford University
Enrico Macii , Politecnico di Torino
Antonio Lioy , Politecnico di Torino
Giuseppe Odasso , Politecnico di Torino
Giovanni de Micheli , Stanford University
Massimo Poncino , Politecnico di Torino
pp. 331

On the Characterization of Multi-Point Nets in Electronic Designs (Abstract)

Fadi J. Kurdahi , University of California Irvine
Dirk Stroobandt , University of Ghent
pp. 344
Formal Verification

HOOVER: Hardware Object-Oriented Verification (Abstract)

Khaled M. Elleithy , King Fahd University of Petroleum and Minerals
Mostafa M. Aref , King Fahd University of Petroleum and Minerals
pp. 351

MDG-based Verification by Retiming and Combinational Transformations (Abstract)

O. Ait Mohamed , Universite de Montreal
E. Cerny , Universite de Montreal
X. Song , Universite de Montreal
pp. 356
Design Methods

Performance Optimization of Self-Timed Circuits (Abstract)

Mark A. Franklin , Washington University
Prithvi Prabhu , Intel Corp.
pp. 374

Stochastic Evolution Algorithm For Technology Mapping (Abstract)

Habib Youssef , King Fahd University of Petroleum and Minerals
Ahmad S. Al-Mulhem , King Fahd University of Petroleum and Minerals
Alaaeldin Amin , King Fahd University of Petroleum and Minerals
pp. 380

RCRS: A Framework for Loop Scheduling with Limited Number of Registers (Abstract)

Edwin H.-M. Sha , University of Notre Dame
Ted Zhihong Yu , University of Notre Dame
Kaisheng Wang , University of Notre Dame
pp. 386

Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example (Abstract)

Sundararajan Sriram , Texas Instruments, Inc.
Dale E. Hocevar , Texas Instruments, Inc.
Dan Pickens , Texas Instruments, Inc.
Ching-Yu Hung , Texas Instruments, Inc.
pp. 400
Low Power

Low Power Driven Scheduling and Binding (Abstract)

Majid Sarrafzadeh , Northwestern University
Jim Crenshaw , Northwestern University
pp. 406

A Methodology for High Level Power Estimation and Exploration (Abstract)

Vamsi Krishna , University of South Florida
N. Ranganathan , University of South Florida
pp. 420
Database for CAD

Sharing Electronic Design Data Via Semantic Spaces (Abstract)

Lois M.L. Delcambre , Oregon Graduate Institute
Satish Venkatesan , Intel Corporation
Karen C. Davis , University of Cincinnati
pp. 432

Standard Data Representations for VLSI Algorithm Development (Abstract)

S. Park , University of Cincinnati
M. Nica , University of Cincinnati
C. Purdy , University of Cincinnati
D. Hertweck , University of Cincinnati
pp. 446

Author Index (PDF)

pp. 459
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