Acknowledgements (PDF)

Organizing Committee (PDF)

GLS-VLSI '98 Program Committee (PDF)

Foreword (PDF)

Message from the Steering Committee Chair (PDF)

Low Power Memory Architectures for Video Applications (Abstract)

Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding (Abstract)

A Low-Power High-Performance Embedded SRAM Macrocell (Abstract)

Low-Power Design of Finite Field Multipliers for Wireless Applications (Abstract)

Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems (Abstract)

A Bootstrapped NMOS Charge Recovery Logic (Abstract)

Power Reducing Techniques for Clocked CMOS PLAs (Abstract)

Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines (Abstract)

A New Full Adder Cell for Low-Power Applications (Abstract)

?-Driven Threshold Elements (Abstract)

A VLSI High-Performance Encoder with Priority Lookahead (Abstract)

Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes (Abstract)

600 MHz Digitally Controlled BiCMOS Oscillator (DCO) for VLSI Signal Processing & Communication Applications (Abstract)

Stability of a Continuous-Time State Variable Filter with OP-AMP and OTA-C Integrators (Abstract)

Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic (Abstract)

CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation (Abstract)

Design of Clock Distribution Networks in Presence of Process Variations (Abstract)

Design of an 8:1 MUX at 1.7Gbit/s in 0.8?m CMOS Technology (Abstract)

Issues in the Design of Domino Logic Circuits (Abstract)

A Novel 1.5-V Cmos Mixer (Abstract)

Analysis of Adaptive CMOS Down Conversion Mixers (Abstract)

Artificial Neural Network Electronic Nose for Volatile Organic Compounds (Abstract)

A VLSI Self-Compacting Buffer for DAMQ Communication Switches (Abstract)

A Dictionary Machine Emulation on a VLSI Computing Tree System (Abstract)

Modeling and Analysis of The Difference-Bit Cache (Abstract)

Modeling of Shift Register-based ATM Switch (Abstract)

An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement (Abstract)

MPEG-2 Video Decoder for DVD (Abstract)

A Self Timed Asynchronous Router for an Heterogeneous Parallel Machine (Abstract)

Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning (Abstract)

Residue to Binary Number Converters for (2^n-1, 2^n, 2^n+1) (Abstract)

The Design of Residue Number System Arithmetic Units for A VLSI Adaptive Equalizer (Abstract)

An Efficient Residue to Weighted Converter for a New Residue Number System (Abstract)

The Chinese Abacus Method: Can We Use It for Digital Arithmetic? (Abstract)

Merged Arithmetic for Computing Wavelet Transforms (Abstract)

Digital Arithmetic Using Analog Arrays (Abstract)

A Combined Interval and Floating Point Multiplier (Abstract)

Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling (Abstract)

Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches (Abstract)

A Unified Approach for a Time-Domain Built-In Self-Test Technique and Fault Detection (Abstract)

VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection (Abstract)

IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits (Abstract)

A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits (Abstract)

Development of a CMOS Cell Library for RF Wireless and Telecommunications Applications (Abstract)

Design Issues of LC Tuned Oscillators for Integrated Transceivers (Abstract)

Novel Simple Models Of Cml Propagation Delay (Abstract)

Next-Generation Narrowband RF Front-Ends in Silicon IC Technology (Abstract)

Low Voltage Low power CMOS AGC circuit for wireless communication (Abstract)

A Continuous-Time Switched-Current $\Sigma\Delta$ Modulator with Reduced Loop Delay (Abstract)

An Exact Input Encoding Algorithm for BDDs Representing FSMs (Abstract)

Maximum Current Estimation in Programmable Logic Arrays (Abstract)

Mutually Disjoint Signals and Probability Calculation in Digital Circuits (Abstract)

Identifying High-Level Components in Combinational Circuits (Abstract)

Local Optimality Theory in VLSI Channel Routing: Composite Cyclic Vertical Constraints (Abstract)

Linear Transformations and Exact Minimization of BDDs (Abstract)

Timed Supersetting and the Synthesis of Telescopic Units (Abstract)

Tabu Search Based Circuit Optimization (Abstract)

On the Characterization of Multi-Point Nets in Electronic Designs (Abstract)

HOOVER: Hardware Object-Oriented Verification (Abstract)

MDG-based Verification by Retiming and Combinational Transformations (Abstract)

Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors (Abstract)

Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS (Abstract)

Performance Optimization of Self-Timed Circuits (Abstract)

Stochastic Evolution Algorithm For Technology Mapping (Abstract)

RCRS: A Framework for Loop Scheduling with Limited Number of Registers (Abstract)

A Quantitative Study of the Benefits of Area-I/O in FPGAs (Abstract)

Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example (Abstract)

Low Power Driven Scheduling and Binding (Abstract)

Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation (Abstract)

A Methodology for High Level Power Estimation and Exploration (Abstract)

How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs (Abstract)

Sharing Electronic Design Data Via Semantic Spaces (Abstract)

VHDL-based EDA Tool Implementation with Java (Abstract)

Standard Data Representations for VLSI Algorithm Development (Abstract)

A Storage Structure for Graph-Oriented Databases Using an Array of Element Types (Abstract)

Author Index (PDF)