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Great Lakes Symposium on VLSI (1996)
Ames, IA
Mar. 22, 1996 to Mar. 23, 1996
ISBN: 0-8186-7502-0
TABLE OF CONTENTS

Reviewers (PDF)

pp. xiii
Session 1A: High-level Synthesis and Special Purpose Architecture I

Loop-List Scheduling for Heterogeneous Functional Units (Abstract)

Yun-Nan Chang , Department of Electrical Engineering University of Minnesota
Ching-Yi Wang , Department of Electrical Engineering University of Minnesota
Keshab K. Parhi , Department of Electrical Engineering University of Minnesota
pp. 0002

Resource-Constrained Algebraic Transformation for Loop Pipelining (Abstract)

Jian-Feng Shi , Dept. of Electrical and Computer Engineering Iowa State University
Liang-Fang Chao , Dept. of Electrical and Computer Engineering Iowa State University
pp. 0014
Session 1B: Circuit Design and FPGA Architecture II

FPGA-based high performance page layout segmentation (Abstract)

N.K. Ratha , Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
A.K. Jain , Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
D.T. Rover , Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
pp. 0029

A Reprogrammable FPGA-Based ATM Traffic Generator (Abstract)

Pong P. Chu , Dept Electrical Engineering Celeveland State University
pp. 0035

Software Fault Tolerance Using Dynamically Reconfigurable FPGAs (Abstract)

Kevin Kwiat , Rome Laboratory
Warren Debany , Rome Laboratory
Salim Hariri , Syracuse University
pp. 0039
Session 2A: Physical Design I

A New Faster Algorithm for Iterative Placement Improvement (Abstract)

Moazzem Hossain , Compass Design Automation San Jose, CA 95131
Bala Thumma , Compass Design Automation San Jose, CA 95131
Sunil Ashtaputre , Compass Design Automation San Jose, CA 95131
pp. 0044

An Accurate Interconnection Length Estimation for Computer Logic (Abstract)

Dirk Stroobandt , University of Ghent, Department of Electronics and Information Systems
Herwig van Marck , University of Ghent, Department of Electronics and Information Systems
Jan van Campenhout , University of Ghent, Department of Electronics and Information Systems
pp. 0050

A Minimum-Area Floorplanning Algorithm for MBC Designs (Abstract)

Dinesh P. Mehta , University of Tennessee Space Institute
Naveed Sherwani , Intel Corporation
pp. 0056
Session 2B: High-level Synthesis and Special Purpose Architecture II
Session 3A: Physical Design II

Chip Pad Migration is a Key Component to High Performance MCM Design (Abstract)

James Loy , United States Military Academy, West Point, NY10996
Atul Garg , United States Military Academy, West Point, NY10996
Mukkai Krishnamoorthy , United States Military Academy, West Point, NY10996
John McDonald , United States Military Academy, West Point, NY10996
pp. 0096
Session 3B: Synthesis and Verification I

Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs (Abstract)

S. Tahar , University of Montreal
Z. Zhou , University of Montreal
X. Song , University of Montreal
E. Cerny , University of Montreal
Michel Langevin , GMD-SET, Shloss Birlinghoven, 53757 St. Augustin, Germany
pp. 0106

Logic Synthesis for Testability (Abstract)

Chien-Chung Tsai , University of California, Santa Barbara, CA 93106
Malgorzata Marek-Sadowska , University of California, Santa Barbara, CA 93106
pp. 0118

Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs (Abstract)

L. Litan , University of Halle, Germany
P. Molitor , University of Halle, Germany
D. Möller , University of Halle, Germany
pp. 0126
Session 4A: Special Session on Issues in Performance Driven Layout

Recent Developments in Performance Driven Steiner Routing: An Overview (Abstract)

Manjit Borah , The Pennsylvania State University
Robert Michael Owens , The Pennsylvania State University
Mary Jane Irwin , The Pennsylvania State University
pp. 0137

Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model (Abstract)

Masato Edahiro , C&C Research Laboratories
Richard J. Lipton , Princeton University
pp. 0143

Simultaneous Routing and Buffer Insertion for High Performance Interconnect (Abstract)

John Lillis , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
Ting-Ting Y. Lin , University of California, San Diego
pp. 0148

Timing and Power Optimization by Gate Sizing Considering False Paths (Abstract)

Guangqiu Chen , Department of Electronics and Communication Kyoto University
Hidetoshi Onodera , Department of Electronics and Communication Kyoto University
Keikichi Tamaru , Department of Electronics and Communication Kyoto University
pp. 0154
Session 4B: Low Power Design

Some Issues in Gray Code Addressing (Abstract)

Huzefa Mehta , Department of Computer Science and Engineering University Park, PA 16802
Robert Michael Owens , Department of Computer Science and Engineering University Park, PA 16802
Mary Jane Irwin , Department of Computer Science and Engineering University Park, PA 16802
pp. 0178
Session 5A: Physical Design III

Transistor Chaining in CMOS Leaf Cells of Planar Topology (Abstract)

Bradley S. Carlson , Dept. of EEDept. of ECE SUNY at Stony Brook Syracuse University
C.Y. Roger Chen , Dept. of EEDept. of ECE SUNY at Stony Brook Syracuse University
Dikran Meliksetian , Dept. of EEDept. of ECE SUNY at Stony Brook Syracuse University
pp. 0194
Session 5B: Testing I

Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits (Abstract)

Sankaran M. Menon , South Dakota School of Mines & Tech
Anura P. Jayasumana , Colorado State University
Yashwant K. Malaiya , Colorado State University
pp. 0214
Session 6A: High-level Synthesis and Special Purpose Architecture III

Design and VLSI Implementation of a Unified Synapse-Neuron Architecture (Abstract)

H. Djahanshahi , University of Windsor
M. Ahmadi , University of Windsor
G.A. Jullien , University of Windsor
W.C. Miller , University of Windsor
pp. 0228

Rapid Prototyping for Fuzzy Systems (Abstract)

C. Chantrapornchai , Dept. of Computer Science and Engineering Notre Dame, IN 46556
S. Tongsima , Dept. of Computer Science and Engineering Notre Dame, IN 46556
E. Sha , Dept. of Computer Science and Engineering Notre Dame, IN 46556
pp. 0234
Session 6B: Circuit Design II

A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh (Abstract)

Jose G. Delgado-Frias , State University of New York
Jabulani Nyathi , State University of New York
Chester L. Miller , State University of New York
Douglas H. Summerville , State University of New York
pp. 0246
Session 7A: Synthesis and Verification II

Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits (Abstract)

Nozar Tabrizi , University of Adelaide
Michael J. Liebelt , University of Adelaide
Kamran Eshraghian , Edith Cowan University
pp. 0266

On Verifying the Correctness of Retimed Circuits (Abstract)

Shi-Yu Huang , University of California, Santa Barbara, CA
Kwang-Ting Cheng , University of California, Santa Barbara, CA
Kuang-Chien Chen , Fujitsu Laboratories of America
pp. 0277
Session 7B: Testing II

On Double Transition Faults as a Delay Fault Model (Abstract)

Irith Pomeranz , Electrical and Computer Engineering Department University of Iowa
Sudhakar M. Reddy , Electrical and Computer Engineering Department University of Iowa
Janak H. Patel , Center for Reliable & High-Performance Computing University of Illinois
pp. 0282

An Efficient Multiple Scan Chain Testing Scheme (Abstract)

Zaifu Zhang , The University of Manitoba
Robert D. McLeod , The University of Manitoba
pp. 0294

Index of Authors (PDF)

pp. 0299
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