The Community for Technology Leaders
Great Lakes Symposium on VLSI (1995)
The State University of New York at Buffalo
Mar. 16, 1995 to Mar. 18, 1995
ISSN: 1066-1395
ISBN: 0-8186-7035-5
TABLE OF CONTENTS

Reviewers List (PDF)

pp. xiv
Session 1A: Synthesis I

Uniform area timing-driven circuit implementation (Abstract)

D. Karayiannis , Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
S. Tragoudas , Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
pp. 2

Optimization using implicit techniques for industrial designs (Abstract)

F. Poirot , Compass Design Autom., Sophia-Antipolis, France
G. Tarroux , Compass Design Autom., Sophia-Antipolis, France
R. Roane , Compass Design Autom., Sophia-Antipolis, France
pp. 8

Optimal technology mapping for single output cells (Abstract)

R. Kolla , Lehrstuhl fur Tech. Inf., Wurzburg Univ., Germany
U. Hinsberger , Lehrstuhl fur Tech. Inf., Wurzburg Univ., Germany
pp. 14
Session 1B: Analog VLSI

A Differential Model Approach To Analog Design Automation (Abstract)

D. J. Klein , School of Electrical Engineering and Computer Science
M. L. Manwaring , School of Electrical Engineering and Computer Science
pp. 22

A new approach for modeling and optimization of analog systems (Abstract)

L. Schelovanov , New Haven Univ., West Haven, CT, USA
E. Penn , New Haven Univ., West Haven, CT, USA
pp. 28

A scalable analog architecture for neural networks with on-chip learning and refreshing (Abstract)

B.A. Alhalabi , Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
M. Bayoumi , Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
pp. 33
Session 2A: Physical Design I

Bus minimization and scheduling of multi-chip systems (Abstract)

M. Sheliga , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
E. Hsing-Mean Sha , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 40

Thumbnail rectilinear Steiner trees (Abstract)

J.L. Ganley , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
J.P. Cohoon , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 46

A two-stage simulated annealing methodology (Abstract)

J.P. Cohoon , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
J.M. Varanelli , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 50

Optimizing wiring space in slicing floorplans (Abstract)

J.T. Mowchenko , Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
Y. Yang , Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
pp. 54
Session 2B: Low Power Design

Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks (Abstract)

E. Macii , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Poncino , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 60

Design and analysis of a low-power energy-recovery adder (Abstract)

W.C. Athas , Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
N. Tzartzanis , Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
pp. 66

Coding a terminated bus for low power (Abstract)

M.R. Stan , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
W.P. Burleson , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 70

Circuit/architecture for low-power high-performance 32-bit adder (Abstract)

I.S. Abu-Khater , VLSI Res. Group, Waterloo Univ., Ont., Canada
M.I. Elmasry , VLSI Res. Group, Waterloo Univ., Ont., Canada
R.H. Yan , VLSI Res. Group, Waterloo Univ., Ont., Canada
A. Bellaouar , VLSI Res. Group, Waterloo Univ., Ont., Canada
pp. 74
Session 3A: Synthesis II

Symbolic execution of data paths (Abstract)

C. Monahan , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
F. Brewer , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 80

Specification and synthesis of bounded indirection (Abstract)

S.D. Johnson , Dept. of Comput. Sci., Indiana Univ., Bloomington, IN, USA
M.E. Tuna , Dept. of Comput. Sci., Indiana Univ., Bloomington, IN, USA
K. Rath , Dept. of Comput. Sci., Indiana Univ., Bloomington, IN, USA
pp. 86

Synthesis of SEU-tolerant ASICs using concurrent error correction (Abstract)

T.D. Bennett , Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
H. Hollander , Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
B.S. Carlson , Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
pp. 90

Scheduling conditional data-flow graphs with resource sharing (Abstract)

J. Siddhiwala , Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Liang-Fang Chao , Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 94
Session 3B: Verification

Automated verification of temporal properties specified as state machines in VHDL (Abstract)

D.S. Fussell , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Y.V. Hoskote , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J.A. Abraham , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 100

Partitioning transition relations efficiently and automatically (Abstract)

M. Langevin , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
X. Song , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
Z. Zhou , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
F. Corella , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
E. Cerny , Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada
pp. 106

Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions (Abstract)

M. Poncino , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
E. Macci , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 112
Session 4A: Physical Design II

An efficient building block layout methodology for compact placement (Abstract)

N.G. Bourbakis , T.J. Watson Sch. of Appl. Sci., Binghamton Univ., NY, USA
M. Mortazavi , T.J. Watson Sch. of Appl. Sci., Binghamton Univ., NY, USA
pp. 118

Performance driven standard-cell placement using the genetic algorithm (Abstract)

S.M. Sait , Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
K. Nassar , Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
M.S.T. Benten , Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
H. Youssef , Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
pp. 124

Priority driven channel pin assignment (Abstract)

P. Molitor , Inst. fur Inf., Halle Univ., Germany
I. Peters , Inst. fur Inf., Halle Univ., Germany
pp. 132
Session 4B: Architecture and Design I

A systolic algorithm and architecture for image thinning (Abstract)

K.B. Doreswamy , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
N. Ranganathan , Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
pp. 138

Analyzing and verifying locally clocked circuits with the concurrency workbench (Abstract)

C. Traver , Dept. of Electr. Eng. & Comput. Sci., Union Coll., Schenectady, NY, USA
G. Baulch , Dept. of Electr. Eng. & Comput. Sci., Union Coll., Schenectady, NY, USA
D. Hemmendinger , Dept. of Electr. Eng. & Comput. Sci., Union Coll., Schenectady, NY, USA
pp. 144

Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs (Abstract)

E. Brunvand , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
Jae-Tack Yoo , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
K.F. Smith , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
pp. 148

A local clocking approach for self-timed datapath designs (Abstract)

R. Sridhar , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
S. Kim , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 152
Session 5A: Synthesis III

A soft computing approach to hardware software codesign (Abstract)

M. Russo , Istituto di Inf. e Telecommun., Catania Univ., Italy
V. Catania , Istituto di Inf. e Telecommun., Catania Univ., Italy
M. Malgeri , Istituto di Inf. e Telecommun., Catania Univ., Italy
N. Fiorito , Istituto di Inf. e Telecommun., Catania Univ., Italy
pp. 158

Technology mapping algorithms for sequential circuits using look-up table based FPGAS (Abstract)

S. Habib , Dept. of Comput. Sci., Graduate Sch. of City Univ. of New York, NY, USA
Quan Xu , Dept. of Comput. Sci., Graduate Sch. of City Univ. of New York, NY, USA
pp. 164

Modeling of communication protocols in VHDL (Abstract)

A. Assi , Ecole Polytech., Montreal, Que., Canada
B. Kaminska , Ecole Polytech., Montreal, Que., Canada
pp. 168

Using EDIF for software generation (Abstract)

D.C. Levy , Dept. of Electr. Eng., Natal Univ., Durban, South Africa
R.G. Harley , Dept. of Electr. Eng., Natal Univ., Durban, South Africa
M.J. Van Der Westhuizen , Dept. of Electr. Eng., Natal Univ., Durban, South Africa
D.R. Woodward , Dept. of Electr. Eng., Natal Univ., Durban, South Africa
pp. 172
Session 5B: Testing

A protocol extraction strategy for control point insertion in design for test of transition signaling circuits (Abstract)

H.E. Li , Dept. of Comput. Sci., Concordia Univ., Montreal, Que., Canada
P.N. Lam , Dept. of Comput. Sci., Concordia Univ., Montreal, Que., Canada
pp. 178

Statistical estimation of delay fault detectabilities and fault grading (Abstract)

R.D. McLeod , Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
Zaifu Zhang , Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
G.E. Bridges , Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
pp. 184

Test application time reduction for scan based sequential circuits (Abstract)

R. Jain , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Hao Zheng , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
K.K. Saluja , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 188

Pseudo-random behavioral ATPG (Abstract)

J.-F. Santucci , LG12P, EMA-EERIE, Nimes, France
A.-L. Courbis , LG12P, EMA-EERIE, Nimes, France
pp. 192
Session 6A: Physical Design III

Fast algorithm for performance-oriented Steiner routing (Abstract)

M. Borah , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 198

OPRON: a new approach to planar OTC routing (Abstract)

S. Danda , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
N. Sherwani , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
S. Madhwapathy , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
A. Sureka , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
pp. 208

Parallel hierarchical global routing for general cell layout (Abstract)

S. Gao , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
K. Thulasiraman , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
S. Khanna , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
pp. 212
Session 6B: Asynchronous Circuits

Improving self-timed pipeline ring performance through the addition of buffer loops (Abstract)

Hai Zhao , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
Edwin Hsing-Mean Sha , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
N.M. Sabine , Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 218

Scan testing of asynchronous sequential circuits (Abstract)

O.A. Petlin , Dept. of Comput. Sci., Oxford Univ., UK
S.B. Furber , Dept. of Comput. Sci., Oxford Univ., UK
pp. 224

A new look at the conditions for the synthesis of speed-independent circuits (Abstract)

E. Pastor , Dept. of Comput. Archit., universitat Politecnica de Catlunya, Barcelona, Spain
J. Cortadella , Dept. of Comput. Archit., universitat Politecnica de Catlunya, Barcelona, Spain
O. Roig , Dept. of Comput. Archit., universitat Politecnica de Catlunya, Barcelona, Spain
pp. 230
Session 7A: VLSI Education

Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT (Abstract)

L.F. Fuller , Dept. of Microelectron. Eng., Rochester Inst. of Technol., NY, USA
C. Kraaijenvanger , Dept. of Microelectron. Eng., Rochester Inst. of Technol., NY, USA
pp. 238

Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test (Abstract)

H.J. Pottinger , Dept. of Electr. Eng., Missouri Univ., Rolla, MO, USA
Chien-Yuh Lin , Dept. of Electr. Eng., Missouri Univ., Rolla, MO, USA
pp. 242

Linking fabrication and parametric testing to VLSI design courses (Abstract)

R. Pearson , Dept. of Microelectron. Eng., Rochester Inst. of Technol., NY, USA
pp. 246

A personal computer based VLSI design curriculum (Abstract)

W.B. Leigh , Div. of Electr. Eng., Alfred Univ., NY, USA
pp. 250
Session 7B: Architecture and Design II

A scalable shared buffer ATM switch architecture (Abstract)

A. Agrawal , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
M.A. Bayoumi , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
A. Raju , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
S. Varadarajan , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 256

ATM burst traffic generator (Abstract)

P.P. Chu , Dept. of Electr. Eng., Cleveland State Univ., OH, USA
pp. 262

A universal formalization of the effects of threshold voltages for discrete switch-level circuit models (Abstract)

W.H.F.J. Korver , Dept. of Electron. & Electr. Eng., Surrey Univ., Guildford, UK
pp. 266

Index of Authors (PDF)

pp. 273
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