Great Lakes Symposium on VLSI (1995)
The State University of New York at Buffalo
Mar. 16, 1995 to Mar. 18, 1995
L.F. Fuller , Dept. of Microelectron. Eng., Rochester Inst. of Technol., NY, USA
C. Kraaijenvanger , Dept. of Microelectron. Eng., Rochester Inst. of Technol., NY, USA
A 2000 transistor p-well CMOS gate array has been designed for use as a teaching tool in the microelectronic engineering program at RIT. Students in microelectronic engineering study integrated circuit design and integrated circuit manufacturing starting in the first year of the five year program. The gate array is manufactured up to level 8 of the 11 level process by students in 5th year manufacturing classes. Levels 8 through 11 include contact cut, metal-one, via and metal-two. These levels are where the gate array is customized. The first year students design simple digital circuits, learn about schematic capture, simulation, bread boarding and layout. They also complete the wafer fabrication as part of their laboratory experience. Students in more advanced courses design more complex analog and digital circuits to be realized using the 2000 transistor gate array. The gate array project has provided an interesting educational experience in design, layout and manufacturing for students from freshmen year to graduate level. The devices function, turn around time is about one week for the last 4 levels of the process.
logic arrays; logic design; integrated circuit design; integrated circuit manufacture; educational aids; electronic engineering education; CMOS logic circuits; p-well CMOS gate array; student run factory; teaching tool; microelectronic engineering program; integrated circuit design; integrated circuit manufacturing; wafer fabrication
L.F. Fuller, C. Kraaijenvanger, "Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT", Great Lakes Symposium on VLSI, vol. 00, no. , pp. 238, 1995, doi:10.1109/GLSV.1995.516059