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Proceedings of 4th Great Lakes Symposium on VLSI (1994)
Notre Dame, IN, USA
March 4, 1994 to March 5, 1994
ISBN: 0-8186-5610-7
TABLE OF CONTENTS

Generation of color-constrained spanning trees with application in symbolic circuit analysis (PDF)

Qicheng Yu , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
C. Sechen , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 252-255

An ADD-based algorithm for shortest path back-tracing of large graphs (PDF)

R.I. Bahar , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
G.D. Hachtel , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
A. Pardo , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
M. Poncino , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
F. Somenzi , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 248-251

An improved algorithm for the generalized min-cut partitioning problem (PDF)

S. Tragoudas , Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
pp. 242-247

A faster dynamic programming algorithm for exact rectilinear Steiner minimal trees (PDF)

J.L. Ganley , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
J.P. Cohoon , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 238-241

Efficient simulation of switch-level circuits in a hierarchical simulation environment (PDF)

J.A. Wehbeh , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
D.G. Saab , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 231-235

Area, performance, and sensitizable paths /spl lsqb/logic design/spl rsqb/ (PDF)

B. Kapoor , Integrated Syst. Lab., Texas Instrum. Inc., Dallas, TX, USA
pp. 222-227

Retiming algorithms with application to VLSI testability (PDF)

D. Kagaris , Comput. Sci. Program, Dartmouth Coll., Hanover, NH, USA
pp. 216-221

Low-power differential CML and ECL BiCMOS circuit techniques (PDF)

K.M. Sharaf , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
M.I. Elmasry , Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
pp. 208-213

Design of a 54-bit adder using a modified Manchester carry chain (PDF)

R. Hashemian , Dept. of Electr. Eng., Northern Illinois Univ., DeKalb, IL, USA
pp. 204-207

Scaling of serially-connected MOSFET chains (PDF)

S.R. Vemuru , Dept. of Electr. Eng., City Coll. of New York, NY, USA
pp. 200-203

An energy-efficient CMOS line driver using adiabatic switching (PDF)

W.C. Athas , Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
J.G. Koller , Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
L.J. Svensson , Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
pp. 196-199

An efficient multiprocessor implementation scheme for real-time DSP algorithms (PDF)

Yu Hen Hu , Dept. of Elect. and Comput. Eng., Wisconsin Univ., WI, USA
Duen-Jeng Wang , Dept. of Elect. and Comput. Eng., Wisconsin Univ., WI, USA
pp. 188-193

Basic building blocks for asynchronous packet routers (PDF)

I.M. Nedelchev , Dept. of Electron. & Electr. Eng., Surrey Univ., Guildford, UK
C.R. Jesshope , Dept. of Electron. & Electr. Eng., Surrey Univ., Guildford, UK
pp. 184-187

Distributed data-path synthesis on a network of workstations (PDF)

M.E. Dalkilic , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 180-183

An efficient algorithm for the realizability analysis of signal transition graphs (PDF)

H.F. Li , Dept. of Comput. Sci., Concordia Univ., Montreal, Que., Canada
S.C. Leung , Dept. of Comput. Sci., Concordia Univ., Montreal, Que., Canada
pp. 174-179

Simulated annealing based yield enhancement of layouts (PDF)

R. Karri , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 166-169

Routability crossing distribution and floating terminal assignment of T-type junction region (PDF)

Jin-Tai Yan , Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Pei-Yung Hsiao , Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 162-165

A gridless multi-layer area router (PDF)

N.K. Sehgal , Intel Corp., Santa Clara, CA, USA
pp. 158-161

Mapping tensor products onto VLSI networks with reduced I/O (PDF)

A. Elnaggar , Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
H.M. Alnuweiri , Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
M.R. Ito , Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
pp. 150-155

VLSI implementation of CORDIC angle units (PDF)

J.-A. Lee , Dept. of Electr. Eng., Houston Univ., TX, USA
M. Ahmad , Dept. of Electr. Eng., Houston Univ., TX, USA
pp. 144-149

Design of transport triggered architectures (PDF)

H. Corporaal , Delft Univ. of Technol., Netherlands
pp. 130-135

A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks (PDF)

J.G. Delgado-Frias , Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA
R. Sze , Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA
H. Summerville , Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA
V. Aikens , Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA
pp. 124-129

Wiring pitch integrates MCM design domains (PDF)

J. Loy , US Mil. Acad., West Point, NY, USA
pp. 120-123

A flow based approach to the pin redistribution problem for multi-chip modules (PDF)

D. Chang , Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
T.F. Gonzalez , Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
O.H. Ibarra , Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
pp. 114-119

Design of a package for a high-speed processor made with yield-limited technology (PDF)

A. Garg , Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
pp. 110-113

A new scheme to compute variable orders for binary decision diagrams (PDF)

J. Jain , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J. Bitner , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
D. Moundanos , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
J.A. Abraham , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
D.S. Fussell , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 105-108

Communication based multilevel synthesis for multi-output Boolean functions (PDF)

P. Molitor , Dept. of Comput. Sci., Humboldt-Univ., Berlin, Germany
pp. 101-104

FPGA-based synthesis of FSMs through decomposition (PDF)

W.L. Yang , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
R.M. Owen , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin , Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
pp. 97-100

Symbolic traversals of data paths with auxiliary variables (PDF)

G. Cabodi , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Camurati , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
S. Quer , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 93-96

A performance driven logic synthesis system using delay estimator (PDF)

Y. Chen , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
Wei Kang Tsai , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
J. Kurdahi , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
T. Her , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
C. Ramachandran , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 88-92

Mathematical model for routability analysis of FPGAs (PDF)

D. Bhatia , Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
pp. 76-79

Generalized segmented channel routing (PDF)

V. Shankar , Design Automation Lab., Cincinnati Univ., OH, USA
D. Bhatia , Design Automation Lab., Cincinnati Univ., OH, USA
pp. 64-69

An algorithm-base fault tolerance (more than one error) using concurrent error detection for FFT processors (PDF)

Chin-Chien Sha , Dept. of Electr. & Comput. Eng., Missouri Univ., Columbia, MO, USA
R.W. Leavene , Dept. of Electr. & Comput. Eng., Missouri Univ., Columbia, MO, USA
pp. 56-61

Structural fault tolerance in VLSI-based systems (PDF)

Hung-Kuei-Ku , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
J.P. Hayes , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 50-55

A new systolic architecture for pipeline prime factor DFT-algorithm (PDF)

S.G. Sedukhin , Dept. of Comput. Sci., Univ. of Aizu, Aizu-Wakamatsu City, Japan
pp. 40-45

Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures (PDF)

D.P. Mehta , Dept. of Comput. Sci., Tennessee Univ. Space Inst., Tullahoma, TN, USA
pp. 34-37

Convergence analyses of simulated evolution algorithms (PDF)

Chi-Yu Mao , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Yu Hen Hu , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 30-33

Floorplanning for mixed macro block and standard cell designs (PDF)

A. Shanbhag , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
S. Danda , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
N. Sherwani , Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
pp. 26-29

Floorplan area optimization using genetic algorithms (PDF)

M. Rebaudengo , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 22-25

Automated system partitioning for synthesis of multi-chip modules (PDF)

R.V. Cherabuddi , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
M.A. Bayoumi , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 15-20

Optimizing cyclic data-flow graphs via associativity (PDF)

Liang-Fang Chao , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 6-10

A distributed controller for system level integration (PDF)

M. Vashi , Texas Univ., Arlington, TX, USA
V. Raj , Texas Univ., Arlington, TX, USA
H.Y. Youn , Texas Univ., Arlington, TX, USA
pp. 2-5
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