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Proceedings Third Great Lakes Symposium on VLSI-Design Automation of High Performance VLSI Systems (1993)
Kalamazoo, MI, USA
March 5, 1993 to March 6, 1993
ISBN: 0-8186-3430-8
TABLE OF CONTENTS

A new state assignment technique for asynchronous finite state machines (PDF)

T.-A. Chu , Cirrus Logic Inc., Fremont, CA, USA
N. Mani , Cirrus Logic Inc., Fremont, CA, USA
C.K.C. Leung , Cirrus Logic Inc., Fremont, CA, USA
pp. 139-143

MinMux: a new approach for global minimization of multiplexers in interconnect synthesis (PDF)

T.C. Wilson , Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
M.K. Garg , Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
pp. 132-138

VLSI synthesis of a programmable DWT chip for the optimal choice of a prototype wavelet (PDF)

S. Ganesan , Dept. of Comput. Sci. & Eng., Oakland Univ., Rochester Hills, MI, USA
S. Mahalingam , Dept. of Comput. Sci. & Eng., Oakland Univ., Rochester Hills, MI, USA
S. Nagabhushana , Dept. of Comput. Sci. & Eng., Oakland Univ., Rochester Hills, MI, USA
pp. 127-131

A logic synthesis system based on global dynamic extraction and flexible cost (PDF)

Y. Chen , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
W.K. Tsai , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
F.J. Kurdahi , Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
pp. 123-126

Optimizing carry lookahead adders for semicustom CMOS (PDF)

C.D. Thomborson , Dept. of Comput. Sci., Minnesota Univ., Duluth, MN, USA
Y. Sun , Dept. of Comput. Sci., Minnesota Univ., Duluth, MN, USA
pp. 119-122

Adaptive bounded time windows in an optimistically synchronized simulator (PDF)

A.C. Palaniswamy , Center for Digital Syst. Eng., Cincinnati Univ., OH, USA
P.A. Wilsey , Center for Digital Syst. Eng., Cincinnati Univ., OH, USA
pp. 114-118

Delta -trees of a graph: introduction and formal definition (PDF)

J.K. Davis , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 107-108

Local improvement in Steiner trees (PDF)

F.D. Lewis , Dept. of Comput. Sci., Kentucky Univ., Lexington, KY, USA
W.C.-C. Pong , Dept. of Comput. Sci., Kentucky Univ., Lexington, KY, USA
pp. 105-106

Minmax-cut graph partitioning problems (PDF)

S. Tragoudas , Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
pp. 100-104

A potential-driven approach to constructing rectilinear Steiner trees (PDF)

S.C. Gadre , Louisiana State Univ., Baton Rouge, LA, USA
R. Vaidyanathan , Louisiana State Univ., Baton Rouge, LA, USA
S.Q. Zheng , Louisiana State Univ., Baton Rouge, LA, USA
pp. 95-99

Toward a Steiner engine: enhanced serial and parallel implementations of the iterated 1-Steiner MRST algorithm (PDF)

T. Barrera , Dept. of Comput. Sci., Virginia Univ., Chartlottesville, VA, USA
J. Griffith , Dept. of Comput. Sci., Virginia Univ., Chartlottesville, VA, USA
S.A. McKee , Dept. of Comput. Sci., Virginia Univ., Chartlottesville, VA, USA
G. Robins , Dept. of Comput. Sci., Virginia Univ., Chartlottesville, VA, USA
T. Zhang , Dept. of Comput. Sci., Virginia Univ., Chartlottesville, VA, USA
pp. 90-94

Rapid-prototyping of high-assurance systems (PDF)

R. Auletta , Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
pp. 85-89

Rate-optimal static scheduling for DSP data-flow programs (PDF)

L.-F. Chao , Dept. of Comput. Sci., Princeton Univ., NJ, USA
pp. 80-84

Efficient minimization algorithms for fixed polarity AND/XOR canonical networks (PDF)

C.-C. Tsai , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
M. Marek-Sadowska , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 76-79

Optimal register allocation in high level synthesis (PDF)

S. Aranake , Texas Univ., Arlington, TX, USA
V. Raj , Texas Univ., Arlington, TX, USA
M. Vashi , Texas Univ., Arlington, TX, USA
H.Y. Youn , Texas Univ., Arlington, TX, USA
pp. 71-75

Parallel genetic algorithm for channel routing (PDF)

B.B.P. Rao , Indian Inst. of Sci., Bangalore, India
L.M. Patnaik , Indian Inst. of Sci., Bangalore, India
R.C. Hansdah , Indian Inst. of Sci., Bangalore, India
pp. 69-70

Corner stitching for L-shaped tiles (PDF)

G. Blust , Dept. of Comput. Sci., Tennessee Univ. Space Inst., Tullahoma, TN, USA
D.P. Mehta , Dept. of Comput. Sci., Tennessee Univ. Space Inst., Tullahoma, TN, USA
pp. 67-68

Mixed spanning trees: a technique for performance-driven routing (PDF)

J.S. Salowe , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 62-66

Switchbox routing with movable terminals (PDF)

J. Hamkins , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
D.J. Brown , Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 57-61

A simple method for noise tolerance characterization of digital circuits (PDF)

S. Simovich , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
P. Franzon , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
M. Steer , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 52-56

Locally clocked microprocessor (PDF)

S.J. Muscato , Dept. of Electr. Eng., Rochester Univ., NY, USA
A. Albicki , Dept. of Electr. Eng., Rochester Univ., NY, USA
pp. 47-51

Clock partitioning for testability (PDF)

K.L. Einspahr , Concordia Coll., Seward, NE, USA
pp. 42-46

A parallel VLSI implementation of Viterbi algorithm for accelerated word recognition (PDF)

V. Upadhyaya , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
S.J. Upadhyaya , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 37-41

Neural system design with the integrated neurocomputing architecture (PDF)

P. Mukai , Charles Stark Draper Lab. Inc., Cambridge, MA, USA
M. Busa , Charles Stark Draper Lab. Inc., Cambridge, MA, USA
P. Kazlas , Charles Stark Draper Lab. Inc., Cambridge, MA, USA
pp. 32-36

A VLSI-based digital multilayer neural network architecture (PDF)

Y.-C. Kim , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
M.A. Shanblatt , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
pp. 27-31

C-testable systolic arrays (PDF)

N. Faroughi , Comput. Sci. Dept., California State Univ., Sacramento, CA, USA
pp. 22-26

Delay fault testability evaluation through timing simulation (PDF)

S. Bose , AT&T Bell Lab., Murray Hill, NJ, USA
P. Agrawal , AT&T Bell Lab., Murray Hill, NJ, USA
V.D. Agrawal , AT&T Bell Lab., Murray Hill, NJ, USA
pp. 18-21

Modeling stuck-open faults in CMOS iterative circuits (PDF)

E. Macii , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 14-17

Modeling the vertical constraints in VLSI channel routing (PDF)

A.D. Jovanovic , Dept. of Electr. Eng., Toledo Univ., OH, USA
pp. 11-13

VICTOR: A three-layer over-the-cell router (PDF)

T.W. Strunk , Dept. of Comput. & Inf. Sci., California Univ., Irvine, CA, USA
N.C. Holmes , Dept. of Comput. & Inf. Sci., California Univ., Irvine, CA, USA
pp. 6-10

Minimizing channel density with movable terminals (PDF)

R.I. Greenberg , Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
J.-D. Shih , Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
pp. 1-5
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