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Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
TABLE OF CONTENTS

Optimum Steiner tree generation (PDF)

F.D. Lewis , Dept. of Comput. Sci., Kentucky Univ., Lexington, KY, USA
Wang Chia-Chi Pong , Dept. of Comput. Sci., Kentucky Univ., Lexington, KY, USA
N. Van Cleave , Dept. of Comput. Sci., Kentucky Univ., Lexington, KY, USA
pp. 207-212

The Steiner tree problem with minimum number of vertices in graphs (PDF)

K. Makki , Dept. of Comput. Sci., Nevada Univ., Las Vegas, NV, USA
pp. 204-206

Clock tree regeneration (PDF)

Jan-ming Ho , Inst. of Inf. Sci., Acad. Sinica, Taipei, Taiwan
pp. 198-203

T-algorithm-based logic simulation on distributed systems (PDF)

S. Sundaram , Indian Inst. of Sci., Bangalore, India
L.M. Patnaik , Indian Inst. of Sci., Bangalore, India
pp. 191-195

Axiomatic semantics of a hardware specification language (PDF)

Xin Hua , Dept. of Comput. Sci., Iowa Univ., Iowa City, IA, USA
Hantao Zhang , Dept. of Comput. Sci., Iowa Univ., Iowa City, IA, USA
pp. 183-190

On the detection and elimination of superfluous level-sensitive latches (PDF)

G. Jennings , Dept. of Comput. Eng., Lund Univ., Sweden
pp. 176-182

Interface constrained processor specification and scheduling (PDF)

J. Greenbaum , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
F. Brewer , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 168-175

A signed hypergraph model of constrained via minimization (PDF)

C.J.-R. Shi , Dept. of Comput. Sci., Waterloo Univ., Ont., Canada
pp. 159-166

Routing in a rectangle with k-ary overlap (PDF)

J. Hamkins , Beckman Inst., Illinois Univ., Urbana, IL, USA
D.J. Brown , Beckman Inst., Illinois Univ., Urbana, IL, USA
pp. 144-151

A new algorithm for signal flow determination in CMOS VLSI (PDF)

A.R. Baba-ali , CDTA-Lab. de Microelectron., Alger, Algeria
pp. 138-141

A systematic approach for designing systolic arrays (PDF)

C.N. Zhang , Dept. of Comput. Sci., Regina Univ., Sask., Canada
A.G. Law , Dept. of Comput. Sci., Regina Univ., Sask., Canada
A. Rezazadeh , Dept. of Comput. Sci., Regina Univ., Sask., Canada
pp. 130-137

An alternative algorithm for high speed multiplication and addition using growing technique (PDF)

R. Hashemian , Dept. of Electr. Eng., Northern Illinois Univ., De Kalb, IL, USA
pp. 124-129

VLSI implementation of controllers for communication protocols from their Petri net models (PDF)

A.M.T. Khan , King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
S.M. Sait , King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
G.F. Beckhoff , King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
pp. 114-121

Self-timed pipeline with adder (PDF)

J. Compton , Dept. of Electr. Eng., Rochester Univ., NY, USA
A. Albicki , Dept. of Electr. Eng., Rochester Univ., NY, USA
pp. 109-113

An asynchronous multiplier (PDF)

B. Luderman , Dept. of Electr. Eng., Rochester Univ., NY, USA
A. Albicki , Dept. of Electr. Eng., Rochester Univ., NY, USA
pp. 104-108

A new conflict resolving switchbox router (PDF)

Tae Won Cho , Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
S.S. Pyo , Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
J.R. Heath , Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
pp. 95-102

Two-layer via-free routing in channels and switchboxes (PDF)

Kuo-Feng Liao , Northwestern Univ., Evanston, IL, USA
pp. 91-94

Interactive optimal channel router for critical nets (PDF)

A.D. Jovanovic , Dept. of Electr. Eng., Toledo Univ., OH, USA
Y.Y. Yeng , Dept. of Electr. Eng., Toledo Univ., OH, USA
pp. 84-90

Quadtree interconnection network layout (PDF)

S. Bhattacharya , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
S. Kirani , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
W.-T. Tsai , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 74-81

Cutwidth approximation in linear time (PDF)

H.D. Booth , Dept. of Comput. Sci., Tennessee Univ., Knoxville, TN, USA
R. Govindan , Dept. of Comput. Sci., Tennessee Univ., Knoxville, TN, USA
M.A. Langston , Dept. of Comput. Sci., Tennessee Univ., Knoxville, TN, USA
S. Ramachandramurthi , Dept. of Comput. Sci., Tennessee Univ., Knoxville, TN, USA
pp. 70-73

High performance data-path synthesis via communication metrics (PDF)

A. Seawright , California Univ., Santa Barbara, CA, USA
F. Brewer , California Univ., Santa Barbara, CA, USA
pp. 60-67

Models for bit-true simulation and high-level synthesis of DSP applications (PDF)

M. Pauwels , IMEC vzw, Heverlee, Belgium
D. Lanneer , IMEC vzw, Heverlee, Belgium
F. Catthoor , IMEC vzw, Heverlee, Belgium
G. Goossens , IMEC vzw, Heverlee, Belgium
H. De Man , IMEC vzw, Heverlee, Belgium
pp. 52-59

A heuristic for data path synthesis using multiport memories (PDF)

I. Ahmad , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
C.Y.R. Chen , Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
pp. 44-51

Performance driven placement with global routing for macro cells (PDF)

A. Lim , Inf. Technol. Inst., Singapore, Singapore
Yeow Meng Chee , Inf. Technol. Inst., Singapore, Singapore
pp. 35-41

The parallel complexity of minimizing column conflicts (PDF)

J.E. Savage , Dept. of Comput. Sci., Brown Univ., Providence, RI, USA
pp. 30-34

Examining routing solutions (PDF)

S. Bapat , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
J.P. Cohoon , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
P.L. Heck , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
A. Ju , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
L.J. Randall , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 24-29

A chip solution to hierarchical and boundary-scan compatible board level BIST (PDF)

O.F. Haberl , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
T. Kropf , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 16-21

A design for concurrent error detections in FPLAs (PDF)

Tsin-Yuan Chang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Jean-Bean Hsu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Chi Wang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Yu-Shen Lin , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 9-15
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