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Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 4-8
P. Johannes , IMEC, Leuven, Belgium
ABSTRACT
A novel solution for the efficiency problems encountered in static timing verification is presented. The LSP algorithm is submitted to a critical analysis. A new hierarchy based approach is presented and its advantages and limitations are highlighted. Finally, some results on real life circuits are presented.<>
INDEX TERMS
built-in self test, circuit analysis computing, VLSI
CITATION

P. Johannes, L. Claesen and H. De Man, "On the use of hierarchy in timing verification with statically sensitizable paths," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 4-8.
doi:10.1109/GLSV.1992.218372
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