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Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 9-15
Tsin-Yuan Chang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Jean-Bean Hsu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Chi Wang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Yu-Shen Lin , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
ABSTRACT
A combined design of four concurrent error detection (CED) schemes-the alternating logic scheme, duplication of the on-set scheme, duplication of the off-set scheme, and the parity checking scheme, is proposed for field programmable logic arrays (FPLAs) which inherently has unutilized elements. One of the four CED schemes can be implemented by the proposed circuit and the unutilized elements with the constraint that the unused elements can be programmed as parts of test logic.<>
INDEX TERMS
error detection, logic arrays, logic testing
CITATION

Tsin-Yuan Chang, Jean-Bean Hsu, Cheng-Chi Wang and Yu-Shen Lin, "A design for concurrent error detections in FPLAs," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 9-15.
doi:10.1109/GLSV.1992.218371
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