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Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 16-21
O.F. Haberl , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
T. Kropf , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
ABSTRACT
To achieve the full benefit of self test approaches, current self test techniques aimed at chip level must be extended to whole boards and systems. The self test must be hierarchical and compatible to the standardized boundary-scan architecture. A hierarchical boundary-scan architecture is presented together with the necessary controller chip and the synthesis software which make a hierarchical self test of arbitrary depth possible and provide sophisticated diagnosis features in case of failure detection.<>
INDEX TERMS
built-in self test, integrated circuit testing, printed circuit testing
CITATION

O. Haberl and T. Kropf, "A chip solution to hierarchical and boundary-scan compatible board level BIST," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 16-21.
doi:10.1109/GLSV.1992.218370
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