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Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 30-34
J.E. Savage , Dept. of Comput. Sci., Brown Univ., Providence, RI, USA
ABSTRACT
Two-layer channel routers typically require a post-processing phase to reduce or eliminate column conflicts. Attempts have been made to parallelize this problem using local search heuristics that swap horizontal channel wire segments. The authors show that all such heuristics for this problem are P-hard and unlikely to be efficiently parallelizable.<>
INDEX TERMS
circuit layout CAD, computational complexity
CITATION

J. Savage and M. Wloka, "The parallel complexity of minimizing column conflicts," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 30-34.
doi:10.1109/GLSV.1992.218368
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