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Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 35-41
A. Lim , Inf. Technol. Inst., Singapore, Singapore
Yeow Meng Chee , Inf. Technol. Inst., Singapore, Singapore
ABSTRACT
The authors present an effective performance driven placement with global routing algorithm for macro cells. Their algorithm is a hierarchical, divide and conquer, quad-partitioning approach. The quad-partitioning routine uses the Tabu search technique. Their algorithm uses the concept of proximity of regions to approximate the interconnection delays during the placement process. In addition, their algorithm can handle modules whose positions are fixed or are restricted to a particular subregion on the layout frame. The experimental results indicate the superiority of their placement in terms of quality of solutions and run times when compared to those by I. Lin and D. Du (1990).<>
INDEX TERMS
circuit layout CAD, search problems, VLSI
CITATION

A. Lim, Yeow Meng Chee and Ching-Ting Wu, "Performance driven placement with global routing for macro cells," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 35-41.
doi:10.1109/GLSV.1992.218367
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