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Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 52-59
M. Pauwels , IMEC vzw, Heverlee, Belgium
D. Lanneer , IMEC vzw, Heverlee, Belgium
F. Catthoor , IMEC vzw, Heverlee, Belgium
G. Goossens , IMEC vzw, Heverlee, Belgium
H. De Man , IMEC vzw, Heverlee, Belgium
ABSTRACT
Real-time DSP applications require a bit-true synthesis system to generate correct and efficient ASICs. This requires concise simulation and synthesis models, which are presented in this paper and exemplified for a non-restoring division operation. Such models are used in the synthesis library of bit-true Cathedral-II compiler, by which industrial size applications have been synthesised.<>
INDEX TERMS
application specific integrated circuits, circuit layout CAD, digital signal processing chips
CITATION

M. Pauwels, D. Lanneer, F. Catthoor, G. Goossens and H. De Man, "Models for bit-true simulation and high-level synthesis of DSP applications," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 52-59.
doi:10.1109/GLSV.1992.218365
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