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Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 70-73
H.D. Booth , Dept. of Comput. Sci., Tennessee Univ., Knoxville, TN, USA
R. Govindan , Dept. of Comput. Sci., Tennessee Univ., Knoxville, TN, USA
M.A. Langston , Dept. of Comput. Sci., Tennessee Univ., Knoxville, TN, USA
S. Ramachandramurthi , Dept. of Comput. Sci., Tennessee Univ., Knoxville, TN, USA
ABSTRACT
Graph width metrics have been widely studied for their relevance to VLSI design. Examples include cutwidth, pathwidth, bandwidth and several others that arise in circuit layout. When the width is bounded, graphs that satisfy these metrics can often be recognized by finite lists of obstruction tests. One of the most foundational tests is to determine whether K/sub 4/ is immersed in a graph. The authors present for the first time a fast, practical algorithm to perform this test, and discuss its relevance to cutwidth and other metrics.<>
INDEX TERMS
circuit layout CAD, graph theory, VLSI
CITATION

H. Booth, R. Govindan, M. Langston and S. Ramachandramurthi, "Cutwidth approximation in linear time," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 70-73.
doi:10.1109/GLSV.1992.218363
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