The Community for Technology Leaders
Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 74-81
S. Bhattacharya , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
S. Kirani , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
W.-T. Tsai , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
ABSTRACT
Quadtree data structure has been used in a number of applications. However, VLSI embedding of quadtree based parallel architecture using grid model has not been studied. This paper studies VLSI embedding of quadtree using grid model. H-tree layout for binary tree is extended for trivial quadtree layout, followed by two layout strategies for rectangular grids. Two generic layout styles (standard layout and X-layout) are proposed for higher order grids (e.g., hexagonal and octagonal grids). Base tile layout patterns are proposed for area compaction with recursive X-layout. In each case, layout dimensions and I/O bandwidth are computed. The authors demonstrate how the two generic layouts can be mixed to obtain higher I/O bandwidth and estimate the area sacrifice. An improved recursive layout mixing strategy is proposed.<>
INDEX TERMS
circuit layout CAD, data structures, VLSI
CITATION

S. Bhattacharya, S. Kirani and W. Tsai, "Quadtree interconnection network layout," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 74-81.
doi:10.1109/GLSV.1992.218362
97 ms
(Ver 3.3 (11022016))