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Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 104-108
B. Luderman , Dept. of Electr. Eng., Rochester Univ., NY, USA
A. Albicki , Dept. of Electr. Eng., Rochester Univ., NY, USA
ABSTRACT
This paper discusses the design and performance of an 8-bit asynchronous multiplier. Self-timed adders with carry completion signals were implemented to create the asynchronous function of the multiplier. The technique of using bi-directional adders is incorporated in the design. One objective of this design was to estimate the longest multiplication time for a 2 mu m CMOS implementation of this 8-bit multiplier.<>
INDEX TERMS
CMOS integrated circuits, digital arithmetic, multiplying circuits
CITATION

B. Luderman and A. Albicki, "An asynchronous multiplier," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 104-108.
doi:10.1109/GLSV.1992.218358
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