Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
J. Compton , Dept. of Electr. Eng., Rochester Univ., NY, USA
A. Albicki , Dept. of Electr. Eng., Rochester Univ., NY, USA
This paper describes the design of an asynchronous pipeline structure comprising a ripple carry adder and registers placed before and after the adder. A scheme was created for monitoring the ripple of the cab through the adder. This scheme provides a means of determining when the addition is complete. The design approach uses transmission gate logic throughout. Results of SPICE simulation on the various building blocks of the circuit are presented.<
adders, circuit analysis computing, logic CAD
J. Compton and A. Albicki, "Self-timed pipeline with adder," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 109-113.