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Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 124-129
R. Hashemian , Dept. of Electr. Eng., Northern Illinois Univ., De Kalb, IL, USA
ABSTRACT
An alternative algorithm is presented for multiplication/addition of variable bit-size operands. The algorithm is shown to be fast, and the computational time is variable and dependent on the accuracy requested. The growing nature of the product term, during the course of operation, gives the method some unique computational properties. The algorithm is implemented for the design of 32*32-bit multiplier.<>
INDEX TERMS
digital arithmetic, multiplying circuits
CITATION

R. Hashemian, "An alternative algorithm for high speed multiplication and addition using growing technique," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 124-129.
doi:10.1109/GLSV.1992.218355
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