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Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 176-182
G. Jennings , Dept. of Comput. Eng., Lund Univ., Sweden
ABSTRACT
The author describes an automated technique for defining, identifying, and removing superfluous level-sensitive latches in large circuits which may contain any number of clocks. The technique presented is based on a delay and function independent design methodology for level-sensitive latched circuits having completely general clocking schemes (n clocks, m phases). More precisely, the technique identifies superfluous clock transitions at each latch, so that superfluous clock waveforms may be simplified. If after transformation the clock waveform becomes identically enabled, then the latch itself may be removed and replaced by a dead short. Analysis complexity and experience with an implementation are discussed.<>
INDEX TERMS
circuit analysis computing, logic CAD
CITATION

G. Jennings, "On the detection and elimination of superfluous level-sensitive latches," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 176-182.
doi:10.1109/GLSV.1992.218348
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