The Community for Technology Leaders
Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 198-203
Jan-ming Ho , Inst. of Inf. Sci., Acad. Sinica, Taipei, Taiwan
ABSTRACT
The authors present a clock tree regeneration algorithm for improving both the wirability and performance of VLSI chip designs. After circuit placement, they modify the clock trees originally specified by logic designs utilizing the geometrical information derived from the placement. First, a bipartite bottleneck matching approach is applied to minimize the longest driver to clock pin length. Then a linear assignment approach is used to optimize the total driverpin length. The experimental results are extremely encouraging.<>
INDEX TERMS
circuit layout CAD, clocks, trees (mathematics), VLSI
CITATION

Jan-ming Ho and Ren-Song Tsay, "Clock tree regeneration," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 198-203.
doi:10.1109/GLSV.1992.218345
80 ms
(Ver 3.3 (11022016))