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Proceedings of the Second Great Lakes Symposium on VLSI (1992)
Kalamazoo, MI, USA
Feb. 28, 1992 to Feb. 29, 1992
ISBN: 0-8186-2610-0
pp: 207-212
F.D. Lewis , Dept. of Comput. Sci., Kentucky Univ., Lexington, KY, USA
Wang Chia-Chi Pong , Dept. of Comput. Sci., Kentucky Univ., Lexington, KY, USA
N. Van Cleave , Dept. of Comput. Sci., Kentucky Univ., Lexington, KY, USA
ABSTRACT
Several phases of the VLSI design process use rectilinear Steiner spanning trees in estimating wire length. Since the problem is NP-complete heuristics form the major portion of the collection of algorithms for this problem. Exact solutions are rare and very few have even been implemented. Thus they seem not to be practical. The authors first reduce the feasible solution space so that exact solutions are possible. Then they develop two branch and bound algorithms which achieve exact solutions. Distributing the computation between processors and parallel computation methods are currently being tested in an attempt to extend the size of the problems which can be actually solved.<>
INDEX TERMS
circuit layout CAD, computational complexity, trees (mathematics), VLSI
CITATION

F. Lewis, Wang Chia-Chi Pong and N. Van Cleave, "Optimum Steiner tree generation," Proceedings of the Second Great Lakes Symposium on VLSI(GLSV), Kalamazoo, MI, USA, , pp. 207-212.
doi:10.1109/GLSV.1992.218343
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