The Community for Technology Leaders
Proceedings First Great Lakes Symposium on VLSI (1991)
Kalamazoo, MI, USA
March 1, 1991 to March 2, 1991
ISBN: 0-8186-2170-2
TABLE OF CONTENTS

Interlocked test generation and digital hardware synthesis (PDF)

F.J. Hill , Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
pp. 2-6

VLSI routing on the pipelined hypercube and related networks (PDF)

J. JaJa , Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
pp. 7-11

Design and evaluation of fault tolerance techniques for highly parallel architectures (PDF)

J.A. Abraham , Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 12

Dense layouts for series-parallel circuits (PDF)

M.A. Langston , Dept. of Comput. Sci., Tennessee Univ., Knoxville, TN, USA
S. Ramachandramurthi , Dept. of Comput. Sci., Tennessee Univ., Knoxville, TN, USA
pp. 14-17

Area efficient binary tree layout (PDF)

S. Bhattacharya , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Wei-Tek Tsai , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 18-24

On wiring overlap layouts (PDF)

C. Chiang , Technol. Inst., Northwestern Univ., Evanston, IL, USA
pp. 25-30

I/O bound binary tree layout (PDF)

S. Bhattacharya , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Yoon-Hwa Choi , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Wei-Tek Tsai , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 31-36

A test controller board for TSS (PDF)

K.T. Kornegay , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.W. Brodersen , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 38-42

An innovative user interface for fault simulation systems (PDF)

P.L. Montessoro , CENS-CNR, Politecnico di Torino, Italy
pp. 49-53

A hierarchical multi-level test generation system (PDF)

A. Lioy , Politecnico di Torino, Italy
M. Poncino , Politecnico di Torino, Italy
pp. 54-59

On the complexity of a fault-tolerance model for multicomputer systems (PDF)

A. Duksu Oh , Dept. of Math., St. Mary's Coll. of Maryland, St. Mary's City, MD, USA
pp. 62-67

Algorithm independent data flow mapping on a unified VLSI architecture (PDF)

S. Mahalingham , Dept. of Comput. Sci. & Eng., Oakland Univ., Rochester, MI, USA
S. Ganesan , Dept. of Comput. Sci. & Eng., Oakland Univ., Rochester, MI, USA
pp. 68-73

Transforming disfigured and disoriented areas into routable switchboxes (PDF)

M. Starkey , Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
pp. 82-87

On the generalized channel definition problem (PDF)

T. Gonzalez , Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
pp. 88-91

An efficient tabu search algorithm for graph bisectioning (PDF)

L. Tao , Fac. of Eng. & Comput. Sci., Concordia Univ., Montreal, Que., Canada
Y.C. Zhao , Fac. of Eng. & Comput. Sci., Concordia Univ., Montreal, Que., Canada
K. Thulasiraman , Fac. of Eng. & Comput. Sci., Concordia Univ., Montreal, Que., Canada
M.N.S. Swamy , Fac. of Eng. & Comput. Sci., Concordia Univ., Montreal, Que., Canada
pp. 92-95

A new approach to timing driven partitioning of combinational logic (PDF)

N. Wehn , Darmstadt Univ. of Technol., Inst. for Microelectron. Syst., Germany
M. Glesner , Darmstadt Univ. of Technol., Inst. for Microelectron. Syst., Germany
pp. 96-101

Optimal test set for stuck-at faults in VLSI (PDF)

K.S. Manjunath , Idaho Univ., Moscow, ID, USA
S. Whitaker , Idaho Univ., Moscow, ID, USA
pp. 104-109

Transition count testing of CMOS combinational circuits (PDF)

K.S. Manjunath , Idaho Univ., Moscow, ID, USA
D. Radharkrishnan , Idaho Univ., Moscow, ID, USA
pp. 110-114

An algebraic approach to test generation for sequential circuits (PDF)

A. Lioy , Politecnico di Torino, Italy
E. Macii , Politecnico di Torino, Italy
A.R. Meo , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
pp. 115-120

A low power CMOS correlator (PDF)

J. Canaris , Idaho Univ., Moscow, ID, USA
S. Whitaker , Idaho Univ., Moscow, ID, USA
pp. 122-127

Implementation of fault-tolerant sequential circuits using programmable logic arrays (PDF)

N. Misra , Dept. of Electr. Eng., Michigan Technol. Univ., Houghton, MI, USA
A.K. Goel , Dept. of Electr. Eng., Michigan Technol. Univ., Houghton, MI, USA
pp. 128-131

A CAD tool for designing large, fault-tolerant VLSI arrays (PDF)

P. Poechmueller , Darmstadt Univ. of Technol., Inst. of Microelectron. Syst., Germany
pp. 132-137

A VLSI implementation of a state variable filter algorithm (PDF)

H.J. Herpel , Darmstadt Univ. of Technol., Inst. of Microelectron. Syst., Germany
P. Windirsch , Darmstadt Univ. of Technol., Inst. of Microelectron. Syst., Germany
M. Glesner , Darmstadt Univ. of Technol., Inst. of Microelectron. Syst., Germany
pp. 138-143

A framework for 1-D compaction with forbidden region avoidance (VLSI layout) (PDF)

S.E. Hambrusch , Dept. of Comput. Sci., Purdue Univ., West Lafayette, IN, USA
pp. 146-151

A linear-time heuristic for rectilinear Steiner trees (PDF)

F.D. Lewis , Dept. of Comput. Sci., Kentucky Univ., Lexington, KY, USA
Wang Chia-Chi Pong , Dept. of Comput. Sci., Kentucky Univ., Lexington, KY, USA
N. Van Cleave , Dept. of Comput. Sci., Kentucky Univ., Lexington, KY, USA
pp. 152-156

Routing non-convex grids without holes (PDF)

D. Parks , Transylvania Univ., Lexington, KY, USA
pp. 157-162

Four layer wiring using adjacent-layer vias (PDF)

T.K. Wu , Dept. of Electr. Comput. Eng., Pennysylvania State Univ., University Park, PA, USA
M.L. Brady , Dept. of Electr. Comput. Eng., Pennysylvania State Univ., University Park, PA, USA
pp. 163-168

A VLSI peripheral system for monitoring and stimulating action potentials of cultured neurons (PDF)

M.A. AbuZaid , Dept. of Electr. Eng., Southern Methodist Univ., Dallas, TX, USA
P.V. Vithalani , Dept. of Electr. Eng., Southern Methodist Univ., Dallas, TX, USA
W.M. Gosney , Dept. of Electr. Eng., Southern Methodist Univ., Dallas, TX, USA
pp. 170-175

An architecture design using VLSI building blocks for dynamic programming neural networks (PDF)

Chinchuan Chiu , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
pp. 176-181

Applying Hopfield network to find the minimum cost coverage of a Boolean function (PDF)

P.P. Chu , Dept. of Electr. Eng., Cleveland State Univ., OH, USA
pp. 182-185

High frequency analog circuit design using QuickChip (PDF)

S.G. Burns , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 196-201

A high resolution current stimulating probe for use in neural prostheses (PDF)

C. Kim , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
D. Kang , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
R.B. Brown , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
K.D. Wise , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 202-206

Designing VLSI systolic arrays with complex processing elements (PDF)

C.N. Zhang , Dept. of Comput. Sci., Regina Univ., Sask., Canada
A.G. Law , Dept. of Comput. Sci., Regina Univ., Sask., Canada
A. Rezazadeh , Dept. of Comput. Sci., Regina Univ., Sask., Canada
pp. 207-212

The 60 degrees grid : routing channels in width d/ square root 3 (PDF)

K.D. Powers , Beckman Inst., Illinois Univ., Urbana, IL, USA
pp. 214-219

Topological via minimization and routing (PDF)

A. Abdullah , Univ. of Southern California, Los Angeles, CA, USA
pp. 220-224

An experimental environment for design and analysis of global routing heuristics (PDF)

J. David , Erik Jonsson Sch. of Eng. & Comput. Sci., Texas Univ., Richardson, TX, USA
F. Makedon , Erik Jonsson Sch. of Eng. & Comput. Sci., Texas Univ., Richardson, TX, USA
pp. 225-230

Building block layout based on block compaction and two-adjacent-side channel router (PDF)

S. Yamada , Dept. of Electr. Eng., Osaka Prefecture Univ., Japan
H. Tanabe , Dept. of Electr. Eng., Osaka Prefecture Univ., Japan
pp. 231-236

Test plan generation and concurrent scheduling of tests in the presence of conflicts (PDF)

T.C. Wilson , Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
A. Basu , Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
D.K. Banerji , Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
J.C. Majithia , Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
pp. 243-248

A parallel algorithm for logic simulation on transputer networks (PDF)

S. Srinivas , Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
pp. 249-254

Proving finite state machines correct with an automaton-based method (PDF)

P. Camurati , Dipartimento di Automatica e Inf., Politecnico di Torino, Italy
M. Gilli , Dipartimento di Automatica e Inf., Politecnico di Torino, Italy
P. Prinetto , Dipartimento di Automatica e Inf., Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Automatica e Inf., Politecnico di Torino, Italy
pp. 255-258

Discrete Fourier transform processors using CORDIC (PDF)

Jeong-A Lee , Dept. of Electr. Eng., Houston Univ., TX, USA
Kiseon Kim , Dept. of Electr. Eng., Houston Univ., TX, USA
pp. 260-265

Uni-directional cube-connected cycles (PDF)

S. Bhattacharya , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Hoon-Hwa Choi , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Wei-Tek Tsai , Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
pp. 266-271

A poly to active region VLSI mask alignment test structure (PDF)

T. Ramesh , Dept. of Electr. Eng., Saginaw Valley State Univ., Univ. Center, MI, USA
pp. 278-283

An approach for multilevel logic cell optimization in module generators (PDF)

P. Poechmueller , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 284-289

Gate matrix layout based on hierarchical net-list representations (PDF)

S. Yamada , Dept. of Electr. Eng., Osaka Prefecture Univ., Japan
K. Yamazaki , Dept. of Electr. Eng., Osaka Prefecture Univ., Japan
pp. 290-295

GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematics (PDF)

N. Baha , Microelectron. Lab. CDTA, El-Madania, Algeria
M. Beddiaf , Microelectron. Lab. CDTA, El-Madania, Algeria
A.-K. Gadiri , Microelectron. Lab. CDTA, El-Madania, Algeria
pp. 296-300

A reconstructive approach to automated design synthesis (PDF)

M.R. Wick , Dept. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
B.D. Britt , Dept. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
pp. 307-311

Genetic synthesis: performance-driven logic synthesis using genetic evolution (PDF)

R. Vemuri , Lab. for Digital Design Environ., Cincinnati Univ., OK, USA
R. Vemuri , Lab. for Digital Design Environ., Cincinnati Univ., OK, USA
pp. 312-317

Sequence invariant state machine compiler (PDF)

D. Buehler , Intel Corp., Hillsboro, OR, USA
pp. 318-323

CMOS output buffer waveshaping (PDF)

L. Albertson , Hewlett-Packard Co., Santa Clara, CA, USA
pp. 326-327

Modeling of the transverse delays in modulation-doped heterojunction field-effect transistors (PDF)

Wei Xu , Dept. of Electr. Eng., Michigan Technol. Univ., Houghton, MI, USA
A.K. Goel , Dept. of Electr. Eng., Michigan Technol. Univ., Houghton, MI, USA
pp. 328-329

Gate level representation of ECL circuits for fault modeling (PDF)

S.M. Menon , Dept. of Electr. Eng., Colorado State Univ., Ft. Collins, CO, USA
A.P. Jayasumana , Dept. of Electr. Eng., Colorado State Univ., Ft. Collins, CO, USA
pp. 330-331

'NCHIPSIM'-a microcomputer simulator of NMOS chip performance indicators (PDF)

A.K. Goel , Dept. of Electr. Eng., Michigan Technol. Univ., Houghton, MI, USA
pp. 332-333

Evaluation of silicon-on-sapphire enhancement JFETs for digital applications (PDF)

I.E. Talkhan , Dept. of Electr. & Syst. Eng., Oakland Univ., Rochester, MI, USA
H.S. Abdel-Aty-Zohdy , Dept. of Electr. & Syst. Eng., Oakland Univ., Rochester, MI, USA
pp. 334-335

Study of quaternary logic versus binary logic (PDF)

A.N. Gupte , Dept. of Electr. Eng., Michigan Technol. Univ., Houghton, MI, USA
A.K. Goel , Dept. of Electr. Eng., Michigan Technol. Univ., Houghton, MI, USA
pp. 336-337

Design of fail-safe CMOS logic circuits (PDF)

V. Bobin , Idaho Univ., Moscow, ID, USA
S. Whitaker , Idaho Univ., Moscow, ID, USA
pp. 338-339

Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits (PDF)

A. Basu , Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
T.C. Wilson , Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
D.K. Banerji , Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
J.C. Majithia , Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
pp. 340-341

HADES-high-level architecture development and exploration system (PDF)

P. Poechmueller , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Held , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
N. Wehn , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 342-343
88 ms
(Ver 3.3 (11022016))