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Fault-Tolerant Computing, International Symposium on (1999)
Madison, Wisconsin
June 15, 1999 to June 18, 1999
ISSN: 0731-3071
ISBN: 0-7695-0213-X
pp: 260
Ilker Hamzaoglu , University of Illinois at Urbana-Champaign
Janak H. Patel , University of Illinois at Urbana-Champaign
ABSTRACT
We propose a new design for testability technique, Parallel Serial Full Scan (PSFS), for reducing the test application time for full scan embedded cores. Test application time reduction is achieved by dividing the scan chain into multiple partitions and shifting in the same vector to each scan chain through a single scan in input. The experimental results for the ISCAS89 circuits showed that PSFS technique significantly reduces both the test application time and the amount of test data for full scan embedded cores.
INDEX TERMS
embedded cores, design-for-testability, full scan, test generation, fault simulation
CITATION

J. H. Patel and I. Hamzaoglu, "Reducing Test Application Time for Full Scan Embedded Cores," Fault-Tolerant Computing, International Symposium on(FTCS), Madison, Wisconsin, 1999, pp. 260.
doi:10.1109/FTCS.1999.781060
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