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Fault-Tolerant Computing, International Symposium on (1999)
Madison, Wisconsin
June 15, 1999 to June 18, 1999
ISSN: 0731-3071
ISBN: 0-7695-0213-X
pp: 200
Ranjit Manomohan , University of California at Davis
G. Robert Redinbo , University of California at Davis
A complete source and channel coding system is protected from both channel errors and errors emanating from internal hardware failures by introducing redundancy in the source encoding and decoding procedures as well as infrequently inserting parity symbols generated by a burst-detecting convolutional code. The combined protected system can detect errors in any significant subsystems whether from transmission errors or hardware faults. The arithmetic source coding procedures are augmented with a few checking operations which detect failure effects at each iteration of the algorithm. The normal input symbol sequence has a parity symbol inserted sparsely; every nth symbol is determined by a high-rate burst-detecting convolutional code. These parity values provide end to end error detection for channel and hardware-based errors. The favorable probability of detection performance is evaluated, and the low overhead costs as measured by increased compression length of the modified source coding procedure are determined.
Fault-tolerant data compression, burst-detecting convolutional codes, algorithm-based fault tolerance, hardware failures, combined source channel coding, arithmetic coding
Ranjit Manomohan, G. Robert Redinbo, "Fault Tolerance, Channel Coding and Arithmetic Source Coding Combined", Fault-Tolerant Computing, International Symposium on, vol. 00, no. , pp. 200, 1999, doi:10.1109/FTCS.1999.781051
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