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Fault-Tolerant Computing, International Symposium on (1997)
Seattle, WA
June 25, 1997 to June 27, 1997
ISSN: 0731-3071
ISBN: 0-8186-7831-3
pp: 339
Bharat P. Dave , Department of Electrical Engineering Princeton University, Princeton, NJ 08544
Niraj K. Jha , Department of Electrical Engineering Princeton University, Princeton, NJ 08544
Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, cost and reliability goals. In this paper, we address the problem of hardware-software co-synthesis of fault-tolerant real-time heterogeneous distributed embedded systems. Fault detection capability is imparted to the embedded system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. The reliability and availability of the architecture are evaluated during co-synthesis. Our algorithm allows the user to specify multiple types of assertions for each task. It uses the assertion or combination of assertions which achieves the required fault coverage without incurring too much overhead. We propose new methods to: 1) perform fault tolerance based task clustering 2) derive the best error recovery topology using a small number of extra processing elements, 3) exploit multi-dimensional assertions, and 4) share assertions to reduce the fault tolerance overhead. Our algorithm can tackle multirate systems commonly found in multimedia applications. Application of the proposed algorithm to several real-life telecom transport system examples shows its efficacy.
allocation, distributed systems, embedded systems, hardware-software co-synthesis, scheduling, system synthesis
Bharat P. Dave, Niraj K. Jha, "COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded System Architectures for Low Overhead Fault Tolerance", Fault-Tolerant Computing, International Symposium on, vol. 00, no. , pp. 339, 1997, doi:10.1109/FTCS.1997.614108
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