The Community for Technology Leaders
International Conference on Field Programmable Logic and Applications (2005)
Aug. 24, 2005 to Aug. 26, 2005
ISBN: 0-7803-9362-7
TABLE OF CONTENTS
Papers

CUSTARD - a customisable threaded FPGA soft processor and tools (Abstract)

O. Mencer , Dept. of Comput., Imperial Coll., London, UK
R. Dimond , Dept. of Comput., Imperial Coll., London, UK
W. Luk , Dept. of Comput., Imperial Coll., London, UK
pp. 1-6

Low-cost fully reconfigurable data-path for FPGA-based multimedia processor (Abstract)

S. Perri , Dept. of Electron., Comput. Sci.&Syst., Calabria Univ., Italy
M. Lanuzza , Dept. of Electron., Comput. Sci.&Syst., Calabria Univ., Italy
pp. 13-18

FPGA PLB evaluation using quantified Boolean satisfiability (Abstract)

A.C. Ling , Dept. of Electr.&Comput. Eng., Toronto Univ., Ont., Canada
pp. 19-24

FELIX: using rewriting-logic for generating functionally equivalent implementations (Abstract)

C. Morra , ITIV, Univ. Karlsruhe (TH), Germany
J. Becker , ITIV, Univ. Karlsruhe (TH), Germany
pp. 25-30

Post-placement bdd-based decomposition for FPGAs (Abstract)

S.D. Brown , Altera Toronto Technol. Center, Canada
V. Manohararajah , Altera Toronto Technol. Center, Canada
D.P. Singh , Altera Toronto Technol. Center, Canada
pp. 31-38

Hashing + memory = low cost, exact pattern matching (Abstract)

G. Papadopoulos , Electron.&Comput. Eng. Dept., Crete Tech. Univ., Greece
pp. 39-44

High-speed and memory efficient TCP stream scanning using FPGA (Abstract)

K. Hiraki , Dept. of Comput. Sci., Tokyo Univ., Japan
M. Inaba , Dept. of Comput. Sci., Tokyo Univ., Japan
Y. Sugawara , Dept. of Comput. Sci., Tokyo Univ., Japan
pp. 45-50

Mutable codesign for embedded protocol processing (Abstract)

T. Sproull , Appl. Res. Lab., Washington Univ., St. Louis, WA, USA
pp. 51-56

Exploiting pipelining to tolerate wire delays in a programmable-reconfigurable processor (Abstract)

R.B. Kujoth , Dept. of Electr.&Comput. Eng., Illinois Univ., Urbana, IL, USA
N.R. Carter , Dept. of Electr.&Comput. Eng., Illinois Univ., Urbana, IL, USA
null Chi-Wei Wang , Dept. of Electr.&Comput. Eng., Illinois Univ., Urbana, IL, USA
J.J. Cook , Dept. of Electr.&Comput. Eng., Illinois Univ., Urbana, IL, USA
D.B. Gottlieb , Dept. of Electr.&Comput. Eng., Illinois Univ., Urbana, IL, USA
pp. 57-64

Applying the small-world network to routing structure of FPGAs (Abstract)

T. Sueyoshi , Fac. of Eng., Kumamoto Univ., Japan
H. Tsukiashi , Fac. of Eng., Kumamoto Univ., Japan
M. Iida , Fac. of Eng., Kumamoto Univ., Japan
pp. 65-70

MILP-based placement and routing for dataflow architecture (Abstract)

null Sung Kyu Lim , Sch. of Electr.&Comput. Eng., Georgia Inst. of Technol., USA
null Mongkol Ekpanyapong , Sch. of Electr.&Comput. Eng., Georgia Inst. of Technol., USA
M. Healy , Sch. of Electr.&Comput. Eng., Georgia Inst. of Technol., USA
pp. 71-76

Using DSP blocks for ROM replacement: a novel synthesis flow (Abstract)

G.A. Constantimdes , Dept. of Electron.&Electr. Eng., Imperial Coll., London, UK
G.W. Morris , Dept. of Electron. & Electr. Eng., Imperial Coll., London, UK
P.Y.K. Cheung , Dept. of Electron.&Electr. Eng., Imperial Coll., London, UK
pp. 77-82

An FPGA solver for WSAT algorithms (Abstract)

T. Maruyama , Syst. & Inf. Eng., Tsukuba Univ., Ibaraki, Japan
K. Kanazawa , Syst.&Inf. Eng., Tsukuba Univ., Ibaraki, Japan
pp. 83-88

An efficient and scalable architecture for neural networks with backpropagation learning (Abstract)

P.O. Domingos , Dept. of Electr.&Comput. Eng., IST/INESC-ID, Portugal
F.M. Silva , Dept. of Electr.&Comput. Eng., IST/INESC-ID, Portugal
H.C. Neto , Dept. of Electr.&Comput. Eng., IST/INESC-ID, Portugal
pp. 89-94

Automatic creation of domain-specific reconfigurable CPLDs for SOC (Abstract)

S. Hauck , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
M. Holland , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 95-100

An 11 GHz FPGA with test applications (Abstract)

J.F. McDonald , ECSE Dept., Rensselaer Polytech. Inst., Troy, NY, USA
null Jong-Ru Guo , ECSE Dept., Rensselaer Polytech. Inst., Troy, NY, USA
null Kuan Zhou , ECSE Dept., Rensselaer Polytech. Inst., Troy, NY, USA
M. Chu , ECSE Dept., Rensselaer Polytech. Inst., Troy, NY, USA
R.P. Kraft , ECSE Dept., Rensselaer Polytech. Inst., Troy, NY, USA
C. You , ECSE Dept., Rensselaer Polytech. Inst., Troy, NY, USA
pp. 101-105

Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes (Abstract)

null Francisco-Javier Veredas , Adv. Syst.&Circuits, Infineon Technol. AG, Munich, Germany
M. Scheppler , Adv. Syst.&Circuits, Infineon Technol. AG, Munich, Germany
pp. 106-111

Power and area optimization for multiple restricted multiplication (Abstract)

P.Y.K. Cheung , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
G.A. Constantinides , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
null Nalin Sidahao , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
pp. 112-117

Error modelling of dual fixed-point arithmetic and its application in field programmable logic (Abstract)

C.T. Ewe , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
G.A. Constantinides , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
P.V.K. Cheung , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
pp. 124-129

Real-time Handel-C based implementation of DV decoder (Abstract)

M. Pac , Dept. of Automatics, AGH Univ. of Sci.&Technol., Krakow, Poland
S. Cichon , Dept. of Automatics, AGH Univ. of Sci.&Technol., Krakow, Poland
M. Gorgon , Dept. of Automatics, AGH Univ. of Sci.&Technol., Krakow, Poland
pp. 130-135

Address generation for FPGA RAMS for efficient implementation of real-time video processing systems (Abstract)

N. Lawal , Dept. of Inf. Technol.&Media, Mid Sweden Univ., Sundsvall, Sweden
M. O'Nils , Dept. of Inf. Technol.&Media, Mid Sweden Univ., Sundsvall, Sweden
B. Thornberg , Dept. of Inf. Technol.&Media, Mid Sweden Univ., Sundsvall, Sweden
pp. 136-141

Novel FPGA-based implementation of median and weighted median filters for image processing (Abstract)

P.Y.K. Cheung , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
S.A. Fahmy , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
W. Luk , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
pp. 142-147

A dynamically reconfigurable Bluetooth Base Band Unit (Abstract)

G. Ozari , Microelectron. Lab., Polythecnic Sch. of Sao Paulo Univ., Brazil
M. Strum , Microelectron. Lab., Polythecnic Sch. of Sao Paulo Univ., Brazil
W. Chau , Microelectron. Lab., Polythecnic Sch. of Sao Paulo Univ., Brazil
M. Teruya , Microelectron. Lab., Polythecnic Sch. of Sao Paulo Univ., Brazil
J. Esquiagola , Microelectron. Lab., Polythecnic Sch. of Sao Paulo Univ., Brazil
pp. 148-152

DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices (Abstract)

M. Majer , Dept. of Comput. Sci., Univ. of Erlangen-Nuremberg, Germany
J. Teich , Dept. of Comput. Sci., Univ. of Erlangen-Nuremberg, Germany
A. Ahmadinia , Dept. of Comput. Sci., Univ. of Erlangen-Nuremberg, Germany
C. Bobda , Dept. of Comput. Sci., Univ. of Erlangen-Nuremberg, Germany
pp. 153-158

Measuring and utilizing the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks (Abstract)

A. Ye , Dept. of Electr.&Comput. Eng., Toronto Univ., Ont., Canada
J. Rose , Dept. of Electr.&Comput. Eng., Toronto Univ., Ont., Canada
pp. 159-166

Timing aware interconnect prediction models for FPGAS (Abstract)

S. Balachandran , Dept. of Electr. Eng., Texas Univ., Dallas, TX, USA
D. Bhatia , Dept. of Electr. Eng., Texas Univ., Dallas, TX, USA
pp. 167-172

Multidimensional dynamic programming for homology search (Abstract)

S. Masuno , Syst.&Inf. Eng., Tsukuba Univ., Ibaraki, Japan
T. Maruyama , Syst.&Inf. Eng., Tsukuba Univ., Ibaraki, Japan
Y. Yamaguchi , Syst.&Inf. Eng., Tsukuba Univ., Ibaraki, Japan
pp. 173-178

Real-time generation of three-dimensional motion fields (Abstract)

H. Niitsuma , Syst.&Inf. Eng., Tsukuba Univ., Ibaraki, Japan
T. Maruyama , Syst.&Inf. Eng., Tsukuba Univ., Ibaraki, Japan
pp. 179-184

Evaluation of ray casting on processor like reconfigurable architectures (Abstract)

W. Rosenstiel , WSL/TI, Univ. Tubingen, Germany
T. Schweizer , WSL/TI, Univ. Tubingen, Germany
T. Kuhn , WSL/TI, Univ. Tubingen, Germany
T. Oppold , WSL/TI, Univ. Tubingen, Germany
pp. 185-190

A flexible circuit switched NOC for FPGA based systems (Abstract)

C. Hilton , Electron. Technol. Div., Rincon Res. Corp., Tucson, AZ, USA
pp. 191-196

Energy efficient NoC for best effort communication (Abstract)

G. Smit , Dept. of EEMCS, Twente Univ., Enschede, Netherlands
P. Wolkotte , Dept. of EEMCS, Twente Univ., Enschede, Netherlands
pp. 197-202

Fault tolerant XGFT network on chip for multi processor system on chip circuits (Abstract)

J. Nurmi , Inst. of Digital&Comput. Syst., Tampere Univ. of Technol., Finland
K. Kariniemi , Inst. of Digital&Comput. Syst., Tampere Univ. of Technol., Finland
pp. 203-210

Modular partial reconfigurable in Virtex FPGAs (Abstract)

P. Sedcole , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
pp. 211-216

Configuration merging for adaptive computer applications (Abstract)

N. Kasprzyk , Dept. for Integrated Circuit Design, Tech. Univ. Braunschweig, Germany
pp. 217-222

Context saving and restoring for multitasking in reconfigurable systems (Abstract)

H. Kalte , Sch. of Comput. Sci.&Software Eng., Univ. of Western Australia, Crawley, WA, Australia
pp. 223-228

An FPGA application with high speed serial transceiver running at sub nominal rate (Abstract)

I. Hadzie , Bell Labs, Lucent Technol., Murray Hill, NJ, USA
D. Suvakovic , Bell Labs, Lucent Technol., Murray Hill, NJ, USA
pp. 229-234

FPGA-based implementation and comparison of recursive and iterative algorithms (Abstract)

B. Pimentel , Electron.&Telecommun. Dept., Aveiro Univ., Portugal
I. Skilarova , Electron.&Telecommun. Dept., Aveiro Univ., Portugal
V. Skylarov , Electron.&Telecommun. Dept., Aveiro Univ., Portugal
pp. 235-240

Configurable hardware/software architecture for data acquisition implementation on FPGA (Abstract)

L. Baldez , R&D Technol. Lab, Digital ASICs Hewlett Packard Co., Barcelona, Spain
F. Cardells-Tormo , R&D Technol. Lab, Digital ASICs Hewlett Packard Co., Barcelona, Spain
J. Sempere-Agullo , R&D Technol. Lab, Digital ASICs Hewlett Packard Co., Barcelona, Spain
M. Bautista-Palacios , R&D Technol. Lab, Digital ASICs Hewlett Packard Co., Barcelona, Spain
P.L. Molinet , R&D Technol. Lab, Digital ASICs Hewlett Packard Co., Barcelona, Spain
pp. 241-246

Defect tolerance in multiple-FPGA systems (Abstract)

Z. Hyder , Dept. of Electr. Eng.&Comput. Sci., California Univ., Berkeley, CA, USA
J. Wawrzynek , Dept. of Electr. Eng.&Comput. Sci., California Univ., Berkeley, CA, USA
pp. 247-254

Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement (Abstract)

G.G.F. Lemieux , Dept. of Electr.&Comput. Eng., British Columbia Univ., Canada
A.J. Yu , Dept. of Electr.&Comput. Eng., British Columbia Univ., Canada
pp. 255-262

Heterogeneity exploration for multiple 2D filter designs (Abstract)

P.Y.K. Cheung , Dept. of Electr.&Electron. Eng., London Imperial Coll., UK
G.A. Constantinides , Dept. of Electr.&Electron. Eng., London Imperial Coll., UK
C.-S. Bouganis , Dept. of Electr.&Electron. Eng., London Imperial Coll., UK
pp. 263-268

Ziggurat-based hardware Gaussian random number generator (Abstract)

P.H.W. Leong , Dept. of Comput. Sci.&Eng., Hong Kong Chinese Univ., Shatin, China
null Guanglie Zhang , Dept. of Comput. Sci.&Eng., Hong Kong Chinese Univ., Shatin, China
pp. 275-280

Snow 2.0 IP core for trusted hardware (Abstract)

L. Spaanenburg , Dept. of Inf. Technol., Lund Univ., Switzerland
null Wen Hai Fang , Dept. of Inf. Technol., Lund Univ., Switzerland
T. Johansson , Dept. of Inf. Technol., Lund Univ., Switzerland
pp. 281-286

A novel asynchronous FPGA architecture design and its performance evaluation (Abstract)

null Xin Jia , Cincinnati Univ., OH, USA
R. Vemuri , Cincinnati Univ., OH, USA
pp. 287-292

A programmable logic architecture for prototyping clockless circuits (Abstract)

M. Renaudin , TIMA Lab., Grenoble, France
L. Fesquet , TIMA Lab., Grenoble, France
pp. 293-298

GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips (Abstract)

S. Renane , TIMA Lab., Grenoble, France
A. Baixas , TIMA Lab., Grenoble, France
L. Fesquet , TIMA Lab., Grenoble, France
M. Renaudin , TIMA Lab., Grenoble, France
J. Quartana , TIMA Lab., Grenoble, France
pp. 299-304

A Verilog RTL synthesis tool for heterogeneous FPGAs (Abstract)

J. Rose , Edward S. Rogers Sr. Dept. of Electr.&Comput. Eng., Toronto Univ., Ont., Canada
P. Jamieson , Edward S. Rogers Sr. Dept. of Electr.&Comput. Eng., Toronto Univ., Ont., Canada
pp. 305-310

Compilation and management of phase-optimized reconfigurable systems (Abstract)

W. Luk , Dept. of Comput., Imperial Coll., London, UK
H. Styles , Dept. of Comput., Imperial Coll., London, UK
pp. 311-316

Trident: an FPGA compiler framework for floating-point algorithms (Abstract)

J.L. Tripp , Los Alamos Nat. Lab., NM, USA
J.D. Poznanovic , Los Alamos Nat. Lab., NM, USA
K.D. Peterson , Los Alamos Nat. Lab., NM, USA
C. Ahrens , Los Alamos Nat. Lab., NM, USA
M.B. Gokhale , Los Alamos Nat. Lab., NM, USA
pp. 317-322

Programmable and reconfigurable hardware architectures for the rapid prototyping of cellular automata (Abstract)

O. Soffke , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
P. Zipf , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
A. Schumacher , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 329-334

A hardware-in-the-loop system to evaluate the performance of small-world cellular automata (Abstract)

O. Soffke , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
P. Zipf , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
C. Schlachta , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
A. Schumacher , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 335-340

Generation and exploration of reconfigurable architectures using mathematical programming (Abstract)

A.M. Smith , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
G.A. Constantinides , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
P.K.K. Cheung , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
pp. 341-346

An I/O mechanism on a dynamically reconfigurable processor - which should be moved: data or configuration? (Abstract)

H. Amano , Dept. of Inf.&Comput. Scinece, Keio Univ., Tokyo, Japan
K. Deguchi , Dept. of Inf.&Comput. Scinece, Keio Univ., Tokyo, Japan
S. Abe , Dept. of Inf.&Comput. Scinece, Keio Univ., Tokyo, Japan
Y. Hasegawa , Dept. of Inf.&Comput. Scinece, Keio Univ., Tokyo, Japan
pp. 347-352

Cluster architecture for reconfigurable signal processing engine for wireless communication (Abstract)

H. Fujisawa , Adv. Mobile Phones Div., Fujitsu Ltd., Kawasaki, Japan
M. Saito , Adv. Mobile Phones Div., Fujitsu Ltd., Kawasaki, Japan
pp. 353-359

Communication synthesis in a multiprocessor environment (Abstract)

C. Zissulescu , Leiden Univ., Netherlands
B. Kienhuis , Leiden Univ., Netherlands
E. Deprettere , Leiden Univ., Netherlands
pp. 360-365

PGR: a software package for reconfigurable super-computing (Abstract)

T. Hamada , Computational Astrophys. Lab., Inst. of Phys.&Chem. Res., Saitama, Japan
N. Nakasato , Computational Astrophys. Lab., Inst. of Phys.&Chem. Res., Saitama, Japan
pp. 366-373

On-chip communication topology synthesis for shared multi-bus based architecture (Abstract)

null Sujan Pandey , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 374-379

A parallel MPEG-4 encoder for FPGA based multiprocessor SoC (Abstract)

M. Hannikainen , Inst. of Digital&Comput. Syst., Tampere Univ. of Technol., Finland
O. Lehtoranta , Inst. of Digital&Comput. Syst., Tampere Univ. of Technol., Finland
E. Salminen , Inst. of Digital&Comput. Syst., Tampere Univ. of Technol., Finland
T.D. Hamalainen , Inst. of Digital&Comput. Syst., Tampere Univ. of Technol., Finland
A. Kulmala , Inst. of Digital&Comput. Syst., Tampere Univ. of Technol., Finland
pp. 380-385

Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis (Abstract)

M. Janiaut , Lab. d'Instrum. Electronique de Nancy, Vandoeuvre-les-Nancy, France
C. Mannino , Lab. d'Instrum. Electronique de Nancy, Vandoeuvre-les-Nancy, France
Y. Berviller , Lab. d'Instrum. Electronique de Nancy, Vandoeuvre-les-Nancy, France
C. Tanougast , Lab. d'Instrum. Electronique de Nancy, Vandoeuvre-les-Nancy, France
null Hassan Rabah , Lab. d'Instrum. Electronique de Nancy, Vandoeuvre-les-Nancy, France
S. Weber , Lab. d'Instrum. Electronique de Nancy, Vandoeuvre-les-Nancy, France
pp. 386-390

An autonomous FPGA-based emulation system for fast fault tolerant evaluation (Abstract)

M. Garcia-Valderas , Departamento de Tecnologia Electronica, Univ. Carlos III de Madrid, Spain
M. Portela-Garcia , Departamento de Tecnologia Electronica, Univ. Carlos III de Madrid, Spain
C. Lopez-Ongil , Departamento de Tecnologia Electronica, Univ. Carlos III de Madrid, Spain
L. Entrena-Arrontes , Departamento de Tecnologia Electronica, Univ. Carlos III de Madrid, Spain
pp. 397-402

On the reliability evaluation of SRAM-based FPGA designs (Abstract)

T. Arnaout , Inst. fur Technische Informatik, Univ. Stuttgart, Germany
H.-J. Wunderlich , Inst. fur Technische Informatik, Univ. Stuttgart, Germany
O. Heron , Inst. fur Technische Informatik, Univ. Stuttgart, Germany
pp. 403-408

Yield modelling and yield enhancement for FPGAs using fault tolerance schemes (Abstract)

G.A. Constantinides , Dept. of EEE, Imperial Coll. London, UK
N. Campregher , Dept. of EEE, Imperial Coll. London, UK
P.Y.K. Cheung , Dept. of EEE, Imperial Coll. London, UK
pp. 409-414

Fast FPGA placement using space-filling curve (Abstract)

S. Bhattacharjee , Adv. Comput.&Microelectron. Unit, Indian Stat. Inst., Kolkata, India
S. Sur-Kolay , Adv. Comput.&Microelectron. Unit, Indian Stat. Inst., Kolkata, India
P. Banerjee , Adv. Comput.&Microelectron. Unit, Indian Stat. Inst., Kolkata, India
S. Das , Adv. Comput.&Microelectron. Unit, Indian Stat. Inst., Kolkata, India
S.C. Nandy , Adv. Comput.&Microelectron. Unit, Indian Stat. Inst., Kolkata, India
pp. 415-420

Hierarchical placement for large-scale FPAA (Abstract)

D. Anderson , Sch. of Electr.&Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
null Sung Kyu Lim , Sch. of Electr.&Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
I.F. Baskaya , Sch. of Electr.&Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
S. Reddy , Sch. of Electr.&Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 421-426

Architecture-adaptive routability-driven placement for FPGAs (Abstract)

S. Hauck , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
A. Sharma , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 427-432

Generalizing square attack using side-channels of an AES implementation on an FPGA (Abstract)

E. Dottax , Defense Securite, SAGEM, Paris, France
H. Chabanne , Defense Securite, SAGEM, Paris, France
H. Pelletier , Defense Securite, SAGEM, Paris, France
V. Carlier , Defense Securite, SAGEM, Paris, France
pp. 433-437

Real-time feature extraction for high speed networks (Abstract)

A. Choudhary , Dept. of Electr.&Comput. Eng., Northwestern Univ., Evanston, IL, USA
S.O. Memik , Dept. of Electr.&Comput. Eng., Northwestern Univ., Evanston, IL, USA
G. Memik , Dept. of Electr.&Comput. Eng., Northwestern Univ., Evanston, IL, USA
D. Nguyen , Dept. of Electr.&Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 438-443

Bitwise optimised CAM for network intrusion detection systems (Abstract)

S. Yusuf , Dept. of Comput., Imperial Coll. London, UK
W. Luk , Dept. of Comput., Imperial Coll. London, UK
pp. 444-449

High speed/low power architectures for the finite radon transform (Abstract)

S. Chandrasekaran , Sch. of Comput. Sci., Queen's Univ., Belfast, UK
A. Amira , Sch. of Comput. Sci., Queen's Univ., Belfast, UK
pp. 450-455

Towards a reconfigurable tracking system (Abstract)

S.G. Wong , Div. of Electron. Warfare&Radar, Defence Sci.&Technol. Organ., Edinburgh, SA, Australia
pp. 456-462

High performance stereo computation architecture (Abstract)

E.M. Ortigosa , Dept. of Comput. Archit.&Technol., Granada Univ., Spain
S. Mota , Dept. of Comput. Archit.&Technol., Granada Univ., Spain
E. Ros , Dept. of Comput. Archit.&Technol., Granada Univ., Spain
B. del Pino , Dept. of Comput. Archit.&Technol., Granada Univ., Spain
J. Diaz , Dept. of Comput. Archit.&Technol., Granada Univ., Spain
pp. 463-468

An emulation model for sequential ATPG-based bounded model checking (Abstract)

null Qiang Qiang , Dept. of Elec. Engr.&Comp. Sci., Case Western Reserve Univ., Cleveland, OH, USA
D.G. Saab , Dept. of Elec. Engr.&Comp. Sci., Case Western Reserve Univ., Cleveland, OH, USA
pp. 469-474
Papers

A low-cost scalable pipelined reconfigurable architecture for simulation of digital circuits (Abstract)

J.T. de Sousa , INESC-ID, Tech. Univ. of Lisbon, Lisboa, Portugal
V. Goncalves , INESC-ID, Tech. Univ. of Lisbon, Lisboa, Portugal
F. Goncalves , INESC-ID, Tech. Univ. of Lisbon, Lisboa, Portugal
pp. 481-486

An FPGA-based soft multiprocessor system for IPv4 packet forwarding (Abstract)

K. Ravindran , California Univ., Berkeley, CA, USA
K. Keutzer , California Univ., Berkeley, CA, USA
null Yujia Jin , California Univ., Berkeley, CA, USA
N. Satish , California Univ., Berkeley, CA, USA
pp. 487-492

Snort offloader: a reconfigurable hardware NIDS filter (Abstract)

J. Lockwood , Dept. of Comput. Sci.&Eng., Washington Univ. in St. Louis, MO, USA
M. Attig , Dept. of Comput. Sci.&Eng., Washington Univ. in St. Louis, MO, USA
T. Sproull , Dept. of Comput. Sci.&Eng., Washington Univ. in St. Louis, MO, USA
null Haoyu Song , Dept. of Comput. Sci.&Eng., Washington Univ. in St. Louis, MO, USA
pp. 493-498

HAIL: a hardware-accelerated algorithm for language identification (Abstract)

J.W. Lockwood , Appl. Res. Lab., Washington Univ. in St. Louis, MO, USA
A.A. Levine , Appl. Res. Lab., Washington Univ. in St. Louis, MO, USA
C.M. Kastner , Appl. Res. Lab., Washington Univ. in St. Louis, MO, USA
G.A. Covington , Appl. Res. Lab., Washington Univ. in St. Louis, MO, USA
pp. 499-504

A run-time reconfigurable hardware infrastructure for IP-core evaluation and test (Abstract)

R. Siripokarpirom , Dept. of Distributed Syst., Tech. Univ. Hamburg-Harburg, Hamburg, Germany
pp. 505-508

A high performance hardware architecture for an SAD reuse based hierarchical motion estimation algorithm for H.264 video coding (Abstract)

S. Yalcin , Fac. of Eng.&Natural Sci., Sabanci Univ., Istanbul, Turkey
H.F. Ates , Fac. of Eng.&Natural Sci., Sabanci Univ., Istanbul, Turkey
I. Hamzaoglu , Fac. of Eng.&Natural Sci., Sabanci Univ., Istanbul, Turkey
pp. 509-514

Statistical power estimation for FPGAs (Abstract)

E. Boemo , Sch. of Eng., Univ. Autonoma de Madrid, Spain
E. Todorovich , Sch. of Eng., Univ. Autonoma de Madrid, Spain
pp. 515-518

CPU-independent assembler in an FPGA (Abstract)

G. Achery , Lehrstuhl fur Rechnertechnik und Rechnerorganisation Technische Univ. Munchen, Germany
C. Trinitis , Lehrstuhl fur Rechnertechnik und Rechnerorganisation Technische Univ. Munchen, Germany
pp. 519-522

Design and test methodology for a reconfigurable PEM data acquisition electronics system (Abstract)

C. Leong , ProsysLab/INESC-ID, Lisbon, Portugal
J.P. Teixeira , ProsysLab/INESC-ID, Lisbon, Portugal
I.C. Teixeira , ProsysLab/INESC-ID, Lisbon, Portugal
P. Bento , ProsysLab/INESC-ID, Lisbon, Portugal
pp. 523-526

Dynamic reconfiguration with hardwired networks-on-chip on future FPGAs (Abstract)

D. Timmermann , Inst. of Appl. Microelectron.&Comput. Eng., Rostock Univ., Rostock-Warnemuende, Germany
S. Kubisch , Inst. of Appl. Microelectron.&Comput. Eng., Rostock Univ., Rostock-Warnemuende, Germany
A. Herrholtz , Inst. of Appl. Microelectron.&Comput. Eng., Rostock Univ., Rostock-Warnemuende, Germany
R. Hecht , Inst. of Appl. Microelectron.&Comput. Eng., Rostock Univ., Rostock-Warnemuende, Germany
pp. 527-530

Efficient embedded FPL resource usage for RNS-based polyphase DWT filter banks (Abstract)

A. Lloris , Dept. Electron.&Comput. Technol., Granada Univ., Spain
E. Castillo , Dept. Electron.&Comput. Technol., Granada Univ., Spain
A. Garcia , Dept. Electron.&Comput. Technol., Granada Univ., Spain
pp. 531-534

Efficient FPGA implementation of Cordic algorithm for circular and linear coordinates (Abstract)

F. Angarita , Dept. de Ingenieria Electronica, Univ. Politecnica de Valencia, Spain
J. Vails , Dept. de Ingenieria Electronica, Univ. Politecnica de Valencia, Spain
T. Sansaloni , Dept. de Ingenieria Electronica, Univ. Politecnica de Valencia, Spain
A. Perez-Pascual , Dept. de Ingenieria Electronica, Univ. Politecnica de Valencia, Spain
pp. 535-538

Efficient hardware architectures for modular multiplication on FPGAs (Abstract)

C. Paar , Horst Gortz Inst. for IT Security, Ruhr Univ. Bochum, Germany
J. Pelzl , Horst Gortz Inst. for IT Security, Ruhr Univ. Bochum, Germany
D. Narh Amanor , Horst Gortz Inst. for IT Security, Ruhr Univ. Bochum, Germany
pp. 539-542

Energy management in battery-powered sensor networks with reconfigurable computing nodes (Abstract)

R. Vemuri , Dept. of ECECS, Cincinnati Univ., OH, USA
J. Khan , Dept. of ECECS, Cincinnati Univ., OH, USA
pp. 543-546

FPGA implementation of an area-time efficient FIR filter core using a self-clocked approach (Abstract)

J. Javier Martinez , Dpto. Electron., Tecnologfa de Comput. y Proyectos, Univ. Politecnica de Cartagena, Spain
J. Manuel Ferrdndez , Dpto. Electron., Tecnologfa de Comput. y Proyectos, Univ. Politecnica de Cartagena, Spain
E. Javier Garrigos , Dpto. Electron., Tecnologfa de Comput. y Proyectos, Univ. Politecnica de Cartagena, Spain
E. Javier Toledo , Dpto. Electron., Tecnologfa de Comput. y Proyectos, Univ. Politecnica de Cartagena, Spain
pp. 547-550

Optimization of start-up time and quiescent power consumption of FPGAs (Abstract)

U. Kebschull , Dept. of Comput. Sci., Leipzig Univ., Germany
A. Schiefer , Dept. of Comput. Sci., Leipzig Univ., Germany
pp. 551-554

QPF: efficient quadratic placement for FPGAs (Abstract)

null Yonghong Xu , Dept. of Electr.&Comput. Eng., Windsor Univ., Ont., Canada
M.A.S. Khalid , Dept. of Electr.&Comput. Eng., Windsor Univ., Ont., Canada
pp. 555-558

Safe PLD-based programmable controllers (Abstract)

J. Marcos , Dpto. Tecnologia Electronica, Vigo Univ., Spain
J. Alvarez , Dpto. Tecnologia Electronica, Vigo Univ., Spain
pp. 559-562

A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware (Abstract)

K. Danne , Dept. of Comput. Sci., Paderborn Univ., Germany
M. Platzner , Dept. of Comput. Sci., Paderborn Univ., Germany
pp. 568-573

A framework for ODE-based multimodel biochemical simulations on an FPGAs (Abstract)

T. Fukushima , Keio Univ., Yokohama, Japan
Y. Iwaoka , Keio Univ., Yokohama, Japan
H. Amano , Keio Univ., Yokohama, Japan
Y. Osana , Keio Univ., Yokohama, Japan
M. Yoshimi , Keio Univ., Yokohama, Japan
pp. 574-577

Area-efficient 2D shift-variant convolvers for FPGA-based digital image processing (Abstract)

J. Sempere-Agullo , InkJet Commercial Div., Hewlett-Packard, Barcelona, Spain
P.-L. Molinet , InkJet Commercial Div., Hewlett-Packard, Barcelona, Spain
M. Bautista-Palacios , InkJet Commercial Div., Hewlett-Packard, Barcelona, Spain
L. Baldez , InkJet Commercial Div., Hewlett-Packard, Barcelona, Spain
F. Cardells-Tormo , InkJet Commercial Div., Hewlett-Packard, Barcelona, Spain
pp. 578-581

Design and FPGA implementation of an embedded real-time biologically plausible spiking neural network processor (Abstract)

M.J. Pearson , IAS Lab., Univ. of the West of England, Bristol, UK
A.G. Pipe , IAS Lab., Univ. of the West of England, Bristol, UK
L. Gilhesphy , IAS Lab., Univ. of the West of England, Bristol, UK
C. Melhuish , IAS Lab., Univ. of the West of England, Bristol, UK
K. Gurney , IAS Lab., Univ. of the West of England, Bristol, UK
B. Mitchinson , IAS Lab., Univ. of the West of England, Bristol, UK
M. Nibouche , IAS Lab., Univ. of the West of England, Bristol, UK
pp. 582-585

Evaluation strategies for coarse grained reconfigurable architectures (Abstract)

H. Schroder , Dortmund Univ., Germany
H. Lange , Dortmund Univ., Germany
pp. 586-589

FIGARO - an automatic tool flow for designs with dynamic reconfiguration (Abstract)

K. Nasi , Atmel-Hellas, S.A., Athens, Greece
T. Karouhalis , Atmel-Hellas, S.A., Athens, Greece
pp. 590-593

FPGA implementation of a GF(2/sup 2M/) multiplier for use in pairing based cryptosystems (Abstract)

W. Marnane , Dept. of Electr.&Electron. Eng., Univ. Coll. Cork, Ireland
T. Kerins , Dept. of Electr.&Electron. Eng., Univ. Coll. Cork, Ireland
M. Keller , Dept. of Electr.&Electron. Eng., Univ. Coll. Cork, Ireland
pp. 594-597

FPGA's middleware for software defined radio applications (Abstract)

X. Reves , Dept. of Signal Theor.&Commun., Univ. Politecnica de Catalunya, Barcelona, Spain
A. Gelonch , Dept. of Signal Theor.&Commun., Univ. Politecnica de Catalunya, Barcelona, Spain
R. Ferrus , Dept. of Signal Theor.&Commun., Univ. Politecnica de Catalunya, Barcelona, Spain
V. Marojevic , Dept. of Signal Theor.&Commun., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 598-601

Implementation of ranking filters on general purpose and reconfigurable architecture based on high density FPGA devices (Abstract)

D. Milojevic , Service des Systemes Logiques et Numeriques, Univ. Libre de Bruxelles, Belgium
pp. 602-605

Integration of a NOC-based multimedia processing platform (Abstract)

J. Nurmi , Inst. of Digital&Comput. Syst., Tampere Univ. of Technol., Finland
T. Ahonen , Inst. of Digital&Comput. Syst., Tampere Univ. of Technol., Finland
pp. 606-611

LAMP: a tool suite for families of FPGA-based computational accelerators (Abstract)

M.C. Herbordt , Dept. of Electr.&Comput. Eng., Boston Univ., MA, USA
T. Van Court , Dept. of Electr.&Comput. Eng., Boston Univ., MA, USA
pp. 612-617

Low power domain-specific reconfigurable array for discrete wavelet transforms targeting multimedia applications (Abstract)

I. Ahmed , Inst. for Syst. Level Integration, Alba Centre, Livingston, UK
T. Arslan , Inst. for Syst. Level Integration, Alba Centre, Livingston, UK
S. Baloch , Inst. for Syst. Level Integration, Alba Centre, Livingston, UK
pp. 618-621

Parameterized logic power consumption models for FPGA-based arithmetic (Abstract)

A.A. Gaffar , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
G.A. Constantinides , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
J.A. Clarke , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
pp. 626-629

Performance improvements using coarse-grain reconfigurable logic in embedded SOCs (Abstract)

G. Dimitroulakos , Dept. of Electr.&Comput. Eng.,, Patras Univ., Rio, Greece
pp. 630-635

A configuration memory architecture for fast run-time reconfiguration of FPGAs (Abstract)

U. Malik , Sch. of Comput. Sci.&Eng., New South Wales Univ., Sydney, NSW, Australia
O. Diessef , Sch. of Comput. Sci.&Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 636-639

A novel toolset for the development of FPGA-like reconfigurable logic (Abstract)

M. Bennebroek , Philips Res. Labs., Eindhoven, Netherlands
A. Danilin , Philips Res. Labs., Eindhoven, Netherlands
S. Sawitzki , Philips Res. Labs., Eindhoven, Netherlands
pp. 640-643

A reconfigurable perfect-hashing scheme for packet inspection (Abstract)

I. Sourdis , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 644-647

An efficient approach to hide the run-time reconfiguration from SW applications (Abstract)

null Yang Qu , VTT Electron., Oulu, Finland
J.-P. Soininen , VTT Electron., Oulu, Finland
pp. 648-653

An FPGA network architecture for accelerating 3DES - CBC (Abstract)

N.W. Bergmann , Sch. of Inf. Technol.&Electr. Eng., Queensland Univ., Brisbane, Qld., Australia
P.R. Sutton , Sch. of Inf. Technol.&Electr. Eng., Queensland Univ., Brisbane, Qld., Australia
null Chin Mun Wee , Sch. of Inf. Technol.&Electr. Eng., Queensland Univ., Brisbane, Qld., Australia
pp. 654-657

An integrated framework for architecture level exploration of reconfigurable platform (Abstract)

A. Thanailakis , Dep. of Electr.&Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
K. Tatas , Dep. of Electr.&Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
K. Siozios , Dep. of Electr.&Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
D. Soudris , Dep. of Electr.&Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
G. Koutroumpezis , Dep. of Electr.&Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
pp. 658-661

Coping with uncertainty in FPGA architecture design (Abstract)

D. Mendel , Altera Corp., San Jose, CA, USA
M. Mutton , Altera Corp., San Jose, CA, USA
B. Ratchev , Altera Corp., San Jose, CA, USA
pp. 662-665

Finite field division implementation (Abstract)

J.-P. Deschamps , Univ. Rovira i Virgili, Tarragona, Spain
G. Sutler , Univ. Rovira i Virgili, Tarragona, Spain
pp. 670-674

FPGA-aware garbage collection in Java (Abstract)

D. Buytaert , Dept. of Electron.&Inf. Syst., Ghent Univ., Belgium
P. Faes , Dept. of Electron.&Inf. Syst., Ghent Univ., Belgium
M. Christiaens , Dept. of Electron.&Inf. Syst., Ghent Univ., Belgium
D. Strooband , Dept. of Electron.&Inf. Syst., Ghent Univ., Belgium
pp. 675-680

High-throughput reconfigurable computing: design and implementation of an IDEA encryption cryptosystem on the SRC-6E reconfigurable computer (Abstract)

A. Michalski , Dept. of Comput. Sci.&Eng., South Carolina Univ., Columbia, SC, USA
D. Buell , Dept. of Comput. Sci.&Eng., South Carolina Univ., Columbia, SC, USA
pp. 681-686

Magnetic remanent memory structures for dynamically reconfigurable FPGA (Abstract)

G. Cambon , LIRMM, Montpeilier Univ., France
L. Torres , LIRMM, Montpeilier Univ., France
G. Sassatelli , LIRMM, Montpeilier Univ., France
N. Bruchon , LIRMM, Montpeilier Univ., France
pp. 687-690

Mullet - a parallel multiplier generator (Abstract)

K.H. Tsoi , Dept. of Comput. Sci.&Eng., Hong Kong Chinese Univ., China
P.H.W. Leong , Dept. of Comput. Sci.&Eng., Hong Kong Chinese Univ., China
pp. 691-694

Netflow probe intended for high-speed networks (Abstract)

M. Zadnik , Fac. of Inf. Technol., Brno Univ. of Technol., Czech Republic
pp. 695-698

Performance tuning of iterative algorithms in signal processing (Abstract)

Z. Pohl , Inst. of Inf. Theor.&Autom., Acad. of Sci. of the Czech Republic, Prague, Czech Republic
J. Kadlec , Inst. of Inf. Theor.&Autom., Acad. of Sci. of the Czech Republic, Prague, Czech Republic
pp. 699-702

Run-time scheduling for random multi-tasking in reconfigurable coprocessors (Abstract)

P. Benoit , ITIV, Karlsruhe Univ., Germany
J. Becker , ITIV, Karlsruhe Univ., Germany
pp. 703-706

A low-energy FPGA: architecture design and software-supported design flow (Abstract)

K. Siozios , Dep. of Electr.&Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
A. Thanailakis , Dep. of Electr.&Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
D. Soudris , Dep. of Electr.&Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
pp. 707-708

A power-performance scalable FPGA using configurable voltage domains and a design mapping tool (Abstract)

F. Honore , Microsystems Technol. Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA
A. Chandrakasan , Microsystems Technol. Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA
pp. 709-710

An approach to scalable molecular dynamics simulation using supercomputing adaptive processing elements (Abstract)

D.A. Buell , Dept. of Comput. Sci.&Eng., South Carolina Univ., Columbia, SC, USA
L.E. Cordova , Dept. of Comput. Sci.&Eng., South Carolina Univ., Columbia, SC, USA
pp. 711-712

Computer arithmetic synthesis technologies on reconfigurable platforms (Abstract)

K.H. Tsoi , Dept. of Comput. Sci.&Eng., Chinese Univ. of Hong Kong, China
pp. 713-714

Dual fixed-point: an efficient alternative to floating-point computation for DSP applications (Abstract)

null Chun Te Ewe , Dept. of Electr.&Electron. Eng., Imperial Coll. London, UK
pp. 715-716

Efficient execution on reconfigurable devices using concepts of pipelining (Abstract)

F. Dittmann , Heinz Nixdorf Inst., Paderborn Univ., Germany
pp. 717-718

Exploration of heterogeneous reconfigurable architectures (Abstract)

A.M. Smith , Dept. of Electr.&Electron. Eng., London Imperial Coll., UK
pp. 719-720

FPGA finite difference time domain solver for thermal simulation (Abstract)

R. Lopez , Dept. de Electronica y Computacion, Univ. de Santiago de Compostela, Spain
D. Cabello , Dept. de Electronica y Computacion, Univ. de Santiago de Compostela, Spain
E. Pardo , Dept. de Electronica y Computacion, Univ. de Santiago de Compostela, Spain
pp. 721-722

FPGA implementation of an augmented reality application for visually impaired people (Abstract)

J.M. Ferrandez , Dpto. Electronica, Tecnologia de Computadoras y Proyectos, Univ. Politecnica de Cartagena, Spain
E.J. Garrigos , Dpto. Electronica, Tecnologia de Computadoras y Proyectos, Univ. Politecnica de Cartagena, Spain
J.J. Martinez , Dpto. Electronica, Tecnologia de Computadoras y Proyectos, Univ. Politecnica de Cartagena, Spain
E.J. Toledo , Dpto. Electronica, Tecnologia de Computadoras y Proyectos, Univ. Politecnica de Cartagena, Spain
pp. 723-724

FPGA interconnect fault tolerance (Abstract)

N. Campregher , Dept. of Electr.&Electron. Eng., Imperial Coll., London, UK
pp. 725-726

Instruction set extension using Microblaze processor (Abstract)

J. Lazanyi , Dept. of Meas.&Inf. Syst., Budapest Univ. of Technol.&Econ., Hungary
pp. 729-730

Leveraging reconfigurability in the design process (Abstract)

L. Shannon , Dept. of Electr.&Comput. Eng., Toronto Univ., Ont., Canada
pp. 731-732

Mechanoprocessor: modeling the rodent whisker sensory system using FPGA (Abstract)

M.J. Pearson , IAS Lab., Univ. of the West of England, Bristol, UK
pp. 733-734

Next generation architectures and CAD for power aware programmable fabrics (Abstract)

R.P. Bharadwaj , Center for Integrated Circuits&Syst., Texas Univ., Dallas, TX, USA
pp. 735-738

PAHLS: towards run-time synthesis for FPGAs (Abstract)

R. Huang , Dept. of Electr. Comput. Eng.&Comput. Sci., Cincinnati Univ., OH, USA
R. Vemuri , Dept. of Electr. Comput. Eng.&Comput. Sci., Cincinnati Univ., OH, USA
pp. 739-740

Reconfigurable architectures for real-time network anomaly detection (Abstract)

D. Nguyen , Dept. of Electr.&Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 741-742

Requested-QOS driven runtime reconfiguration of mobile devices (Abstract)

H. Joshi , Dept. of Inf. Technol., MLV Textile Inst., Bhilwara, India
S.S. Verma , Dept. of Inf. Technol., MLV Textile Inst., Bhilwara, India
pp. 743-744

Design of a dynamic reconfigurable multi-grained hardware architecture with adaptive runtime routing (Abstract)

A. Thomas , Inst. fur Technik der Informationsverarbeitung, Univ. Karlsruhe, Denmark
pp. 745-746

Testing superscalar processors in functional mode (Abstract)

V. Singh , Nara Inst. of Sci.&Technol., Japan
M. Inoue , Nara Inst. of Sci.&Technol., Japan
pp. 747-748

Author index (PDF)

pp. 751-762
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