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International Conference on Field Programmable Logic and Applications (2005)
Aug. 24, 2005 to Aug. 26, 2005
ISBN: 0-7803-9362-7
pp: 547-550
J. Javier Martinez , Dpto. Electron., Tecnologfa de Comput. y Proyectos, Univ. Politecnica de Cartagena, Spain
E. Javier Toledo , Dpto. Electron., Tecnologfa de Comput. y Proyectos, Univ. Politecnica de Cartagena, Spain
E. Javier Garrigos , Dpto. Electron., Tecnologfa de Comput. y Proyectos, Univ. Politecnica de Cartagena, Spain
J. Manuel Ferrdndez , Dpto. Electron., Tecnologfa de Comput. y Proyectos, Univ. Politecnica de Cartagena, Spain
ABSTRACT
In this paper we propose an area-time efficient architecture for the realization of self-clocked MAC filters on FPGA. First, the self-timed 4-phase oscillator/counter is analyzed and characterized, showing experimental results in comparison with simulation foreseen. Next, the proposed filter architecture, based on circular memories, is described and efficiently implemented as an IP module using device primitives and relative location constraints. Finally, an example using the proposed architecture is implemented on an FPGA and compared with a standard IP filter of similar characteristics, pointing out the advantages of our approach.
INDEX TERMS
IP module, FPGA implementation, FIR filter, self-clocked approach, area-time efficient architecture, MAC filters, self-timed oscillator, self-timed counter, circular memories
CITATION

J. Javier Martinez, J. Manuel Ferrdndez, E. Javier Garrigos and E. Javier Toledo, "FPGA implementation of an area-time efficient FIR filter core using a self-clocked approach," International Conference on Field Programmable Logic and Applications(FPL), vol. 00, no. , pp. 547-550, 2005.
doi:10.1109/FPL.2005.1515782
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