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International Conference on Field Programmable Logic and Applications (2005)
Aug. 24, 2005 to Aug. 26, 2005
ISBN: 0-7803-9362-7
pp: 269-274
S. Virtanen , Dept. of Inf. Technol., Turku Univ., Finland
We present a methodology for synthesizing TTA protocol processors onto CMOS and FPGA from application specifications with reduced designer intervention and a short turn-around time. The methodology builds up on our earlier work in generating synthesizable processor models from system level specifications for 0.18 /spl mu/m CMOS technology. We test the application level methodology by comparing results obtained from a generated FPGA synthesis model to results obtained from a generated CMOS synthesis model. We synthesized an architecture for processing the IPv6 protocol, which resulted in an implementation that achieved the clock speed of 45 MHz. Due to the scalable parallelism of TTA architectures, this corresponds to an approximate throughput of 500 Mbps for IPv6 routing. From the results we were able to conclude that the critical delay in our generated FPGA implementations is formed inside our protocol processing functional units.
0.18 micron, application-specific protocol processors, TTA protocol processor synthesis, system level specifications, CMOS technology, FPGA synthesis model, CMOS synthesis model, IPv6 protocol, parallel TTA architectures, IPv6 routing, 45 MHz

S. Virtanen, J. Paakkulainen, J. Lilius, J. Isoaho and D. Truscan, "Highly automated FPGA synthesis of application-specific protocol processors," International Conference on Field Programmable Logic and Applications(FPL), vol. 00, no. , pp. 269-274, 2005.
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