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Field-Programmable Gate Arrays, International ACM Symposium on (2000)
Monterey, California, USA
Feb. 10, 2000 to Feb. 11, 2000
ISBN: 0-7695-2592-X
TABLE OF CONTENTS
Papers

The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density (Abstract)

Elias Ahmed , University of Toronto, Canada
Jonathan Rose , University of Toronto, Canada
pp. 3-12

Programmable Memory Blocks Supporting Content-Addressable Memory (Abstract)

Kerry Veenstra , Altem, San Jose, CA
Frank Heile , Altem, San Jose, CA
Andrew Leaver , Altem, San Jose, CA
pp. 13-21

A Novel High Throughput Reconfigurable FPGA Architecture (Abstract)

Arindam Mukherjee , University of California, Santa Barbara
Luca Macchiarulo , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Amit Singh , University of California, Santa Barbara
pp. 22-29

An FPGA Implementation and Performance Evaluation of the Serpent Block Cipher (Abstract)

C. Paar , Worcester Polytechnic Institute, MA
AJ Elbirt , Worcester Polytechnic Institute, MA
pp. 33-40

Factoring Large Numbers with Programmable Hardware (Abstract)

Hea Joung Kim , University of California, Los Angeles
William H. Mangione-Smith , University of California, Los Angeles
pp. 41-48

Technology Mapping for k/m-Macrocell Based FPGAs (Abstract)

Xin Yuan , University of California, Los Angeles
Hui Huang , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 51-59

Technology Mapping Issues for an FPGA with Lookup Tables and PLA-like Blocks (Abstract)

Alireza Kaviani , Xilinx Inc., San Jose, CA
Stephen Brown , University of Toronto, Canada
pp. 60-66

Synthesis for FPGAs with Embedded Memory Blocks (Abstract)

Jason Cong , University of California, Los Angeles
Kenneth Yan , University of California, Los Angeles
pp. 75-82

A Reconfigurable Multi-function Computing Cache Architecture (Abstract)

Arun K. Somani , Iowa State University, Ames
Hue-Sung Kim , Iowa State University, Ames
Akhilesh Tyagi , Iowa State University, Ames
pp. 85-94

A C Compiler for a Processor with a Reconfigurable Functional Unit (Abstract)

Prithviraj Banerjee , Northwestern University, Evanston, IL
Zhi Alex Ye , Northwestern University, Evanston, IL
Nagaraj Shenoy , Northwestern University, Evanston, IL
pp. 95-100

The Application of Genetic Algorithms to the Design of Reconfigurable Reasoning VLSI Chips (Abstract)

Ikuo Yoshihara , Miyazaki University
Moritoshi Yasunaga , University of Tsukuba, Japan
Jung Hwan Kim , University of Louisiana, Lafayette, Louisiana
pp. 116-125

A Benchmark Suite for Evaluating Configurable Computing Systems - Status, Reflections, and Future Directions (Abstract)

C. Nanavati , Honeywell Technology Center, Minneapolis, MN
D. Pandalai , Honeywell Technology Center, Minneapolis, MN
L. Pires , Honeywell Technology Center, Minneapolis, MN
S. Kumar , Honeywell Technology Center, Minneapolis, MN
S. Wadi , Honeywell Technology Center, Minneapolis, MN
H. Spaanenburg , Mercury Computer Systems, Inc., Chelmsford, MA
M. Vojta , Honeywell Technology Center, Minneapolis, MN
S. Ponnuswamy , Honeywell Technology Center, Minneapolis, MN
J. Golusky , Honeywell Technology Center, Minneapolis, MN
pp. 126-134

Field Programmable Port Extender (FPX) for Distributed Routing and Queuing (Abstract)

Jon S. Turner , Washington University, Saint Louis, MO
John W. Lockwood , Washington University, Saint Louis, MO
David E. Taylor , Washington University, Saint Louis, MO
pp. 137-144

Implementing a RAKE Receiver for Wireless Communications on an FPGA-based Computer System (Abstract)

Ali M. Shankiti , Motorola, SPS, Mansfield, MA
Miriam Leeser , Northeastern University, Boston, MA
pp. 145-151

Generating Highly-Routable Sparse Crossbars for PLDs (Abstract)

Guy Lemieux , University of Toronto, Canada
David Lewis , University of Toronto, Canada
Paul Leventis , Right Track CAD Corp., Toronto, Canada
pp. 155-164

New Parallelization and Convergence Results for NC: A Negotiation-Based FPGA Router (Abstract)

Pak K. Chan , University of California, Santa Cruz
Martine D. E. Schlag , University of California, Santa Cruz
pp. 165-174

Automatic Generation of FPGA Routing Architectures from High-Level Descriptions (Abstract)

Jonathan Rose , University of Toronto, ON, Canada
Vaughn Betz , Right Track CAD Corp., Toronto, ON
pp. 175-184

Tolerating Operational Faults in Cluster-based FPGAs (Abstract)

Vijay Lakamraju , University of Massachusetts, Amherst, MA
Russell Tessier , University of Massachusetts, Amherst, MA
pp. 187-194

Power Estimation Approach for SRAM-Based FPGAs (Abstract)

Karlheinz WeiB , University of T?bingen, Germany
Thorsten Steckstor , University of T?bingen, Germany
Igor Katchan , University of T?bingen, Germany
Wolfgang Rosenstiel , University of T?bingen, Germany
Carsten Oetker , University of T?bingen, Germany
pp. 195-202

Timing-Driven Placement for FPGAs (Abstract)

Alexander (Sandy) Marquardt , Right Track CAD Corp., Toronto, ON, Canada
Vaughn Betz , Right Track CAD Corp., Toronto, ON, Canada
Jonathan Rose , Right Track CAD Corp., Toronto, ON, Canada
pp. 203-213

Coarse-Grained Carry Architecture for FPGA (PDF)

Hyuk-Jun Lee , Stanford University, Stanford, CA
Michael J. Flynn , Stanford University, Stanford, CA
pp. 217

Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs (PDF)

C. Alippi , Politecnico di Milano, Italy
W. Fornaciari , Politecnico di Milano, Italy
L. Pozzi , Politecnico di Milano, Italy
M. Sami , Politecnico di Milano, Italy
pp. 218

FPGA Implementation and Analysis of Image Restoration (PDF)

F. S. Ogrenci , Northwestern University, Evanston, IL
A. K. Katsaggelos , Northwestern University, Evanston, IL
M. Sarrafzadeh , Northwestern University, Evanston, IL
pp. 219

Low Power Digital Design in FPGAs: A Study of Pipeline Architectures Implemented in a FPGA using a Low Supply Voltage to Reduce Power Consumption (PDF)

Wayne Burleson , University of Massachusetts, Amherst
Andr?s D. Garc?a Garc? , University of Massachusetts, Amherst
Jean Luc Danger , Ecole Nationale Sup?rieure des T?l?communications, France
pp. 220

Reconfigurable Target Recognition System (PDF)

Jason Scott , Vanderbilt University, Nashville, TN
Ted Bapty , Vanderbilt University, Nashville, TN
Gabor Szedo , Vanderbilt University, Nashville, TN
Sandeep Neema , Vanderbilt University, Nashville, TN
pp. 221

Synthesizing Full-Systolic Arrays For Matrix Product On Xilinx's XC4000(E, EX) FPGAs (PDF)

Abdelkrim Kamel Oudjida , CDTA/ Microelectronics and Robotics laboratories, Algiers, Algeria
Sabrina Titri , CDTA/ Microelectronics and Robotics laboratories, Algiers, Algeria
Mustapha Hamarlain , CDTA/ Microelectronics and Robotics laboratories, Algiers, Algeria
pp. 222

Author Index (PDF)

pp. 223
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