The Community for Technology Leaders
Field-Programmable Gate Arrays, International ACM Symposium on (1999)
Monterey, California, USA
Feb. 21, 1999 to Feb. 23, 1999
ISBN: 0-7695-2584-9
TABLE OF CONTENTS
Papers

A New High Density and Very Low Cost Reprogrammable FPGA Architecture (Abstract)

Arun Kundu , Actel Corporation, Sunnyvale, CA
Ben Ting , BTR Inc., Cupertino, CA
Sinan Kaptanoglu , Actel Corporation, Sunnyvale, CA
Greg Bakker , Actel Corporation, Sunnyvale, CA
Ivan Corneillet , Actel Corporation, Sunnyvale, CA
pp. 3-12

Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks (Abstract)

Andrew Leaver , Altera Corporation, San Jose, CA
Frank Heile , Altera Corporation, San Jose, CA
pp. 13-16

An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-Gating Functions (Abstract)

Giap Tran , Vantis Corporation, Sunnyvale, CA
Nick Schmitz , Vantis Corporation, Sunnyvale, CA
Bill Harding , Vantis Corporation, Sunnyvale, CA
Bai Nguyen , Vantis Corporation, Sunnyvale, CA
Herman Chang , Vantis Corporation, Sunnyvale, CA
Jack Wong , Vantis Corporation, Sunnyvale, CA
Om Agrawal , Vantis Corporation, Sunnyvale, CA
Brad Sharpe-Geisler , Vantis Corporation, Sunnyvale, CA
Fabiano Fontana , Vantis Corporation, Sunnyvale, CA
pp. 17-26

Cut Ranking and Pruning: Enabling A General And Efficient FPGA Mapping Solution (Abstract)

Jason Cong , University of California, Los Angeles
Chang Wu , University of California, Los Angeles
Yuzheng Ding , Lucent Technologies, Murray Hill, NJ
pp. 29-35

Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density (Abstract)

Alexander (Sandy) Marquardt , University of Toronto, Canada
Vaughn Betz , University of Toronto, Canada
Jonathan Rose , University of Toronto, Canada
pp. 37-46

A Methodology for Fast FPGA Floorplanning (Abstract)

Dinesh Bhatiat , University of Cincinnati, OH
John M. Emmert , University of Cincinnati, OH
pp. 47-56

FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density (Abstract)

Vaughn Betz , University of Toronto, Canada
Jonathan Rose , University of Toronto, Canada
pp. 59-68

Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures (Abstract)

S.R. Park , University of Massachusetts, Amherst
W. Burleson , University of Massachusetts, Amherst
pp. 81-89

Don't Care Discovery for FPGA Configuration Compression (Abstract)

Scott Hauck , Northwestern University, Evanston, IL
Zhiyuan Li , Northwestern University, Evanston, IL
pp. 91-98

A FPGA-Based Hardware Implementation of Generalized Profile Search Using Online Arithmetic (Abstract)

Emeka Mosanya , Swiss Federal Institute of Technology, Switzerland
Eduardo Sanchez , Swiss Federal Institute of Technology, Switzerland
pp. 101-111

Procedural Texture Mapping on FPGAs (Abstract)

David M. Lewis , University of Toronto
Andy G. Ye , University of Toronto
pp. 112-120

HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array (Abstract)

Omid Rowhani , University of California at Berkeley
William Tsu , University of California at Berkeley
Kip Macy , University of California at Berkeley
Tony Tung , University of California at Berkeley
Varghese George , University of California at Berkeley
Norman Walker , University of California at Berkeley
Atul Joshi , University of California at Berkeley
Andr? DeHon , University of California at Berkeley
John Wawrzynek , University of California at Berkeley
Randy Huang , University of California at Berkeley
pp. 125-134

A Reconfigurable Arithmetic Array for Multimedia Applications (Abstract)

Tony Stansfield , Hewlett Packard Laboratories, UK
lgor Kostarnov , Hewlett Packard Laboratories, UK
Jean Vuillemin , Ecole Normale Superieure, France
Brad Hutchings , Brigham Young University, Provo, Utah
Alan Marshall , Hewlett Packard Laboratories, UK
pp. 135-143

Memory Interfacing and Instruction Specification for Reconfigurable Processors (Abstract)

Jeffrey A. Jacob , University of Toronto, Canada
Paul Chow , University of Toronto, Canada
pp. 145-154

Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs (Abstract)

Yaska Sankar , University of Toronto, Canada
Jonathan Rose , University of Toronto, Canada
pp. 157-166

Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs Via Search-Based Boolean SAT (Abstract)

Gi-Joon Nam , University of Michigan, Ann Arbor
Karem A. Sakallah , University of Michigan, Ann Arbor
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, PA
pp. 167-175

Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems (Abstract)

Abdel Ejnioui , University of South Florida, Tampa, FL
N. Ranganathan , The University of Texas at El Paso
pp. 176-184

Circuit Partitioning for Dynamically Reconfigurable FPGAs (Abstract)

D. F. Wong , University of Texas at Austin
Huiqun Liu , University of Texas at Austin
pp. 187-194

Fast Compilation for Pipelined Reconfigurable Fabrics (Abstract)

Mihai Budiu , Carnegie Mellon University
Seth Copen Goldstein , Carnegie Mellon University
pp. 195-205

Configuration Caching vs Data Caching for Striped FPGAs (Abstract)

Deepali Deshpande , Iowa State University, Ames
Akhilesh Tyagi , Iowa State University, Ames
Arun K. Somani , Iowa State University, Ames
pp. 206-214

String Matching on Multicontext FPGAs using Self-Reconfiguration (Abstract)

Viktor K. Prasanna , University of Southern California, Los Angeles
Alessandro Mei , University of Southern California, Los Angeles
Reetinder P. S. Sidhu , University of Southern California, Los Angeles
pp. 217-226

Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs (Abstract)

B. M. Al-Hashimi , Staffordshire University, UK
P. Kollig , Staffordshire University, UK
pp. 227-234

Exploiting FPGA-Features during the Emulation of a Fast Reactive Embedded System (Abstract)

Wolfgang Rosenstiel , University of T?bingen, Germany
Gemot Koch , University of T?bingen, Germany
Thorsten Steckstor , University of T?bingen, Germany
Karlheinz Weiss , University of T?bingen, Germany
pp. 235-242

Architecture Considerations for Mixed Signals FPGAs (PDF)

Luigi Carro , Universidade Federal do Rio Grande do Sul, Brasil
pp. 245

A Computational Intelligence Based Coarse-Grained Reconfigurable Element (PDF)

Robert D. McLeod , University of Manitoba, Winnipeg, Canada
C. Hart Poskar , University of Manitoba, Winnipeg, Canada
Peter J. Czezowski , University of Manitoba, Winnipeg, Canada
pp. 246

Extra-Dimensional Island-Style FPGAs (PDF)

Herman Schmit , Carnegie Mellon University
pp. 247

FPGA-Targeted Development System for Embedded Applications (PDF)

J. Fonseca , Aveiro University (Portugal)
V. Sklyarov , Aveiro University (Portugal)
A. Melo , Aveiro University (Portugal)
K. Kondratjuk , Aveiro University (Portugal)
P. Neves , Aveiro University (Portugal)
A. Oliveira , Aveiro University (Portugal)
A. Ferrari , Aveiro University (Portugal)
N. Lau , Aveiro University (Portugal)
I. Skliarova , Aveiro University (Portugal)
R. Monteiro , Aveiro University (Portugal)
pp. 248

High-Performance Low-Cost Implementation of Two-dimensional DCT Processor nn FPGA (PDF)

L. Naviner , Ecole Nationale Superieure des Telecommunications, France
C. Laurent , Ecole Nationale Superieure des Telecommunications, France
J-L. Danger , Ecole Nationale Superieure des Telecommunications, France
pp. 249

Implementing an Artificial CPG using Fine-Grain FPGAs (PDF)

Felipe M. G. Franca , Universidade Federal do Rio de Janeiro, Brazil
Zhijun Yang , Universidade Federal do Rio de Janeiro, Brazil
pp. 250

Partitioning Large Designs by Filling FPGA Devices with Hierarchy Blocks (PDF)

Helena Krupnova , CSI/Institut National Polytechnique de Grenoble, France
Gabriele Saucier , CSI/Institut National Polytechnique de Grenoble, France
pp. 251

Universal Switch Blocks for Three-Dimensional FPGA Design (PDF)

Guang-Ming Wu , National Chiao Tung University, Hsinchu, Taiwan
Yao-Wen Chang , National Chiao Tung University, Hsinchu, Taiwan
Michael Shyu , National Chiao Tung University, Hsinchu, Taiwan
pp. 254

The X-MatchLITE FPGA-Based Data Compressor (PDF)

Stephen Bateman , GateField Corporation, Fremont, CA
Jose Luis Nunez , Loughborough University, England
Claudia Feregrino , Loughborough University, England
Simon Jones , Loughborough University, England
pp. 255
91 ms
(Ver 3.1 (10032016))