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Field-Programmable Gate Arrays, International ACM Symposium on (1997)
Monterey, California, United States
Feb. 9, 1997 to Feb. 11, 1997
ISBN: 0-89791-801-0
TABLE OF CONTENTS
Papers

Architecture Issues and Solutions for a High-Capacity FPGA (Abstract)

Steve Trimberger , Xilinx, Inc.
Bob Conn , Xilinx, Inc.
Khue Duong , Xilinx, Inc.
pp. 3-9

Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays (Abstract)

Jonathan Rose , University of Toronto
Zvonko G. Vranesic , University of Toronto
Steven J.E. Wilton , University of British Columbia
pp. 10-16

Laser Correcting Defects to Create Transparent Routing for Large Area FPGA's (Abstract)

Benoit Dufort , Simon Fraser University
G. H. Chapman , Simon Fraser University
pp. 17-23

Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping (Abstract)

Jason Cong , University of California at Los Angeles
Yean-Yow Hwang , University of California at Los Angeles
pp. 35-42

General Modeling and Technology-Mapping Technique for LUT-Based FPGAs (Abstract)

Amit Chowdhary , University of Michigan
John P. Hayes , University of Michigan
pp. 43-49

The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System (Abstract)

Paul Chow , University of Toronto
Marcus van Ierssel , University of Toronto
David M. Lewis , University of Toronto
Jonathan Rose , University of Toronto
David R. Galloway , University of Toronto
pp. 53-61

Module Generation of Complex Macros for Logic-Emulation Applications (Abstract)

Allen C.-H. Wu , Tsing Hua University
Wen-Jong Fang , Tsing Hua University
Duan-Ping Chen , Quickturn Design Systems, Inc.
pp. 69-75

Wormhole Run-Time Reconfiguration (Abstract)

Peter Athanas , Virginia Polytechnic Institute and State University
Ray Bittner , Virginia Polytechnic Institute and State University
pp. 79-85

Improving Functional Density through Run-Time Constant Propagation (Abstract)

Michael J. Wirthlin , Brigham Young University
Brad L. Hutchings , Brigham Young University
pp. 86-92

YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing (Abstract)

Akihiro Tsutsui , IT Optical Nehvork Systems Laboratories
Toshiaki Miyazaki , ITSystem Electronics Laboratories
pp. 93-100

Is Reconfigurable Computing Commercially Viable (Panel)? (PDF)

Robert Colwell , Intel Corp.
Robert Parker , ITO, DARPA
Peter Athanas , Virginia Polytechnic Institute
Steve Casselman , Virtual Computer Corp.
Herman Schmit , Carnegie Mellon University
Daryl Eigen , Metalithic Systems, Inc.
pp. 101

Synthesis and Floorplanning for Large Hierarchical FPGAs (Abstract)

C. Rabedaoro , Institut National Polytechnique de Grenoble/CSI
H. Krupnova , Institut National Polytechnique de Grenoble/CSI
G. Saucier , Institut National Polytechnique de Grenoble/CSI
pp. 105-111

Performance Driven Floorplanning for FPGA Based Designs (Abstract)

Jianzhong Shi , University of Cincinnati
Dinesh Bhatia , University of Cincinnati
pp. 112-118

FPGA Routing and Routability Estimation via Boolean Satisfiability (Abstract)

Rob A. Rutenbar , Carnegie Mellon University
R. Glenn Wood , Carnegie Mellon University
pp. 119-125

Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond (Abstract)

Jonathan Rose , University of Toronto
Dwight Hill , University of Toronto and Synopsys Inc.
pp. 129-132

A CMOS Continuous-Time Field Programmable Analog Array (Abstract)

C. Lyden , University College Cork
C. A. Looby , University College Cork
pp. 137-141

Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs (Abstract)

Malgorzata Marek-Sadowska , University of California at Santa Barbara
Douglas Chang , University of California at Santa Barbara
pp. 142-148

Generation of Synthetic Sequential Benchmark Circuits (Abstract)

Jonathan Rose , University of Toronto
Michael Hutton , University of Toronto
Derek Corneil , University of Toronto
pp. 149-155

Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size (Abstract)

Miloš D. Ercegovac , University of California at Los Angeles
Alexandre F. Tenca , University of California at Los Angeles
pp. 159-163

A FPGA-Based Implementation of a Fault-Tolerant Neural Architecture for Photon Identification (Abstract)

E. L. Gummati , Universitá degli Studi di Milano
G. R. Sechi , Istituto di Fisica Cosmica e TecnologieRelative, Consiglio Nazionale delle Ricerche
M. Alderighi , Istituto di Fisica Cosmica e TecnologieRelative, Consiglio Nazionale delle Ricerche
V. Piuri , Politecnico di Milano
pp. 166-172
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