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Field-Programmable Gate Arrays, International ACM Symposium on (1996)
Monterey, California, USA
Feb. 11, 1996 to Feb. 13, 1996
ISBN: 0-7695-2576-8
TABLE OF CONTENTS
Papers

Hybrid FPGA Architecture (Abstract)

Alireza Kaviani , University of Toronto, Canada
Stephen Brown , University of Toronto, Canada
pp. 3-9

Plasma: An FPGA for Million Gate Systems (Abstract)

R. Amerson , Hewlett-Packard Laboratories
R. Carter , Hewlett-Packard Laboratories
W. Culbertson , Hewlett-Packard Laboratories
P. Kuekes , Hewlett-Packard Laboratories
G. Snider , Hewlett-Packard Laboratories
Lyle Albertson , Hewlett-Packard California Design Center
pp. 10-16

Flexible FPGA Architecture realized of General Purpose SOG (Abstract)

Kengo Azegami , Fujitsu Laboratories Ltd., Japan
Shoichiro Kashiwakura , Fujitsu Laboratories Ltd., Japan
Koichi Yamashita , Fujitsu Laboratories Ltd., Japan
pp. 17-22

Using BDDs to Design ULMs for FPGAs (Abstract)

Zeljko Zilic , University of Toronto
Zvonko G. Vranesic , University of Toronto
pp. 24-30

Universal Logic Modules for Series-Parallel Functions (Abstract)

Shashidhar Thakur , University of Texas at Austin
D. F. Wong , University of Texas at Austin
pp. 31-37

Combined Spectral Techniques for Boolean Matching (Abstract)

E. Schubert , Universit?t T?bingen, Germany
W. Rosenstiel , Universit?t T?bingen, Germany
pp. 38-43

The Wave Pipeline Effect on LUT-Based FPGA Architectures (Abstract)

Eduardo I. Boemo , Ciudad Universitaria, Madrid - Espa?
Sergio L?pez-Buedo , Ciudad Universitaria, Madrid - Espa?
Juan M. Meneses , Ciudad Universitaria, Madrid - Espa?
pp. 45-50

Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays (Abstract)

Vi Cuong Chan , University of Toronto
David M. Lewis , University of Toronto
pp. 51-57

Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance (Abstract)

Peichen Pan , Clarkson University, Potsdam, NY
C. L. Liu , University of Illinois at Urbana-Champaign
pp. 58-64

Entropy, Counting, and Programmable Interconnect (Abstract)

Andr? DeHon , MIT Artificial Intelligence Laboratory, Cambridge, MA
pp. 73-79

Universal Switch-Module Design for Symmetric-Array-Based FPGAs (Abstract)

Yao-Wen Chang , University of Texas at Austin
D. F. Wong , University of Texas at Austin
C. K. Wong , Chinese University of Hong Kong
pp. 80-86

Design and Implementation of a Field Programmable Analogue Array (Abstract)

Adrian Bratt , Pilkington Micro-electronics Limited (PMeL), Cheshire, UK
Ian Macbeth , Pilkington Micro-electronics Limited (PMeL), Cheshire, UK
pp. 88-93

Diagnosing Programmable Interconnect Systems for FPGAs (Abstract)

Fabrizio Lombardi , Texas A&M University, College Station, TX
David Ashen , Texas A&M University, College Station, TX
Xiaotao Chen , Texas A&M University, College Station, TX
Wei Kang Huang , Fudan University, P.R. China
pp. 100-106

Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks (Abstract)

Charles Stroud , University of Kentucky
Ping Chen , University of Kentucky
Srinivasa Konala , University of Kentucky
Miron Abramovici , AT&T Bell Laboratories, Murray Hill, NJ
pp. 107-113

DPGA Utilization and Application (Abstract)

Andr? DeHon , MIT Artificial Intelligence Laboratory, Cambridge, MA
pp. 115-121

Sequencing Run-Time Reconfigured Hardware with Software (Abstract)

Michael J. Wirthlin , Brigham Young University, Provo, UT
Brad L. Hutchings , Brigham Young University, Provo, UT
pp. 122-128

Computing the Discrete Fourier Transform on FPGA Based Systolic Arrays (Abstract)

Chris Dick , La Trobe University, Australia
pp. 129-135

RASP: A General Logic Synthesis System for SRAM-Based FPGAs (Abstract)

Jason Cong , University of California, Los Angeles
John Peck , University of California, Los Angeles
Yuzheng Ding , AT&T Bell Laboratories, Murray Hill, NJ
pp. 137-143

Emerald - An Architecture-Driven Tool Compiler for FPGAs (Abstract)

Darren C. Cronquist , University of Washington, Seattle, WA
Larry McMurchie , University of Washington, Seattle, WA
pp. 144-150
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