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Field-Programmable Gate Arrays, International ACM Symposium on (1996)
Monterey, California, USA
Feb. 11, 1996 to Feb. 13, 1996
ISBN: 0-7695-2576-8
pp: 24-30
Zeljko Zilic , University of Toronto
Zvonko G. Vranesic , University of Toronto
Many modern FPGAs use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. Since permutations and negation of signals are virtually costless operations in FPGAs, it is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs. Such blocks, known as Universal Logic Modules (ULMs), have only recently been considered for application in FPGAs. In this paper we propose a class of ULMs useful in the FPGA environment. Methodology for systematic development of such blocks is presented, based on BDD description of logic functions. We give an explicit construction of a 3-input LUT replacement that requires only 5 programming bits, which is the optimum for such ULMs. A realistic size 4-input LUT replacement is obtained which uses 13 programming bits. Such logic blocks are especially important when FPGAs are used in a reconfigurable manner, because they can reduce the time and memory needed for changing the configuration.

Z. G. Vranesic and Z. Zilic, "Using BDDs to Design ULMs for FPGAs," Field-Programmable Gate Arrays, International ACM Symposium on(FPGA), Monterey, California, USA, 1996, pp. 24-30.
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