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Field-Programmable Gate Arrays, International ACM Symposium on (1995)
Monterey, California, USA
Feb. 12, 1995 to Feb. 14, 1995
ISBN: 0-7695-2550-4
TABLE OF CONTENTS
Papers

On Designing ULM-Based FPGA Logic Modules (Abstract)

D. F. Wong , University ofTexas at Austin
Shashidhar Thakur , University ofTexas at Austin
pp. 3-9

Using Architectural "Families" to Increase FPGA Speed and Density (Abstract)

Vaughn Betz , University of Toronto, Canada
Jonathan Rose , University of Toronto, Canada
pp. 10-16

Design of FPGAs with Area I/O for Field Programmable MCM (Abstract)

Wayne Wei-Ming Dai , UC Santa Cruz
Vijayshri Maheshwari , UC Santa Cruz
John Ramirez , UC Santa Cruz
Joel Darnauer , UC Santa Cruz
pp. 17-23

TIERS: Topology IndependEnt Pipelined Routing and Scheduling for VirtualWire™ Compilation (Abstract)

Matt Dahl , Virtual Machine Works, Inc., Cambridge, MA
Jonathan Babb , Virtual Machine Works, Inc., Cambridge, MA
Anant Agarwal , Virtual Machine Works, Inc., Cambridge, MA
Charles Selvidge , Virtual Machine Works, Inc., Cambridge, MA
pp. 25-31

Logic Partition Orderings for Multi-FPGA Systems (Abstract)

Scott Hauck , University of Washington, Seattle, WA
Gaetano Borriello , University of Washington, Seattle, WA
pp. 32-38

An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays (Abstract)

R. Ziegler , University of Missouri - Rolla
W. Eatherton , University of Missouri - Rolla
L. R. Mullin , University of Missouri - Rolla
J. Kelly , University of Missouri - Rolla
H. Pottinger , University of Missouri - Rolla
T. Schiefelbein , University of Missouri - Rolla
pp. 39-45

High-Energy Physics on DECPeRLe-1 Programmable Active Memory (Abstract)

Jean Vuillemin , P?le Universitaire L?onard-de-Vinci, LaD?fense, France
Philippe Boucard , Matra-Harris Semiconductors, Saint-Quentin-en-Yvelines, France
Laurent Moll , Ecole Nationale Sup?rieure des T?l?communications, Paris, France
pp. 47-52

HGA: A Hardware-Based Genetic Algorithm (Abstract)

Stephen D. Scott , Washington University, St. Louis, MO
Ashok Samal , University of Nebraska-Lincoln
Sharad Seth , University of Nebraska-Lincoln
pp. 53-59

The Design of RPM: An FPGA-based Multiprocessor Emulator (Abstract)

Krishnan Ramamurthy , University of Southern California, Los Angeles, CA
Sasan Iman , University of Southern California, Los Angeles, CA
Luiz A. Barroso , University of Southern California, Los Angeles, CA
Michel Dubois , University of Southern California, Los Angeles, CA
Koray ?ner , University of Southern California, Los Angeles, CA
Jaeheon Jeong , University of Southern California, Los Angeles, CA
pp. 60-66

Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping (Abstract)

Jason Cong , University of California, Los Angeles, CA
Yean-Yow Hwang , University of California, Los Angeles, CA
pp. 68-74

Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses (Abstract)

Baher Haroun , Concordia University, Quebec, Canada
Behzad Sajjadi , Concordia University, Quebec, Canada
pp. 75-81

On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping (Abstract)

Yuzheng Ding , UCLA Computer Science Department, Los Angeles, CA
Jason Cong , UCLA Computer Science Department, Los Angeles, CA
pp. 82-88

Architecture of Centralized Field-Configurable Memory (Abstract)

Zvonko G. Vranesic , University of Toronto, Canada
Jonathan Rose , University of Toronto, Canada
Steven J. E. Wilton , University of Toronto, Canada
pp. 97-103

A Field-Programmable Mixed-Analog-Digital Array (Abstract)

P. Glenn Gulak , University of Toronto, Canada
Paul Chow , University of Toronto, Canada
Paul Chow , University of Toronto, Canada
pp. 104-109

PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs (Abstract)

Larry McMurchie , University of Washington, Seattle, WA
Carl Ebeling , University of Washington, Seattle, WA
pp. 111-117

Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs (Abstract)

Anmol Mathur , U. of Illinois, Urbana-Champaign
K. C. Chen , Fujitsu America Inc., San Jose, CA
C. L. Liu , U. of Illinois, Urbana-Champaign
pp. 118-124

Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays (Abstract)

Wei Kang Huang , Fudan University, Shanghai, P.R. China
Fabrizio Lombardi , Texas A&M University, College Station, TX
Tong Liu , Texas A&M University, College Station, TX
pp. 125-131

Spectral-Based Multi-Way FPGA Partitioning (Abstract)

Pak K. Chan , University of California, Santa Cruz
Jason Y. Zien , University of California, Santa Cruz
Martine D. F. Schlag , University of California, Santa Cruz
pp. 133-139

Multi-Way System Partitioning into a Single Type or Multiple Types of FPGAs (Abstract)

Dennis J.-H. Huang , UCLA Computer Science Department, Los Angeles, CA
Andrew B. Kahng , UCLA Computer Science Department, Los Angeles, CA
pp. 140-145

Multiple FPGA Partitioning with Performance Optimization (Abstract)

Carl Sechen , University of Washington, Seattle, WA
Kalapi Roy-Neogi , University of Washington, Seattle, WA
pp. 146-152

Techniques for FPGA Implementation of Video Compression Systems (Abstract)

Rajeev Jain , University of California, Los Angeles
Steve Molloy , University of California, Los Angeles
Brian Schoner , University of California, Los Angeles
John Villasenor , University of California, Los Angeles
pp. 154-159

An SBus Monitor Board (Abstract)

D. Leask , The University of Melbourne, Australia
K. E. Forward , The University of Melbourne, Australia
H. A. Xie , The University of Melbourne, Australia
K. M. Adams , The University of Melbourne, Australia
pp. 160-167

High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems (Abstract)

Tsuyoshi Isshiki , University of California, Santa Cruz
Wayne Wei-Ming Dai , University of California, Santa Cruz
pp. 167-173
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