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Proceedings of 1993 IEEE 34th Annual Foundations of Computer Science (1993)
Palo Alto, CA, USA
Nov. 3, 1993 to Nov. 5, 1993
ISBN: 0-8186-4370-6
pp: 341-350
C. Kaklamanis , DIMACS Center, Rutgers Univ., Piscataway, NJ, USA
ABSTRACT
The existence of bounded degree networks which can emulate the computation of any bounded degree network of the same size with logarithmic slowdown is well-known. The butterfly is an example of such a universal network. Leiserson was the first to introduce the concept of an area-universal network: a network with VLSI layout area A which can emulate any network of the same size and layout area with logarithmic slowdown. His results imply the existence of an N-node network with layout area O(N log/sup 2/ N) which can emulate any N-node planar network with O(log N) slowdown. The main results of this paper are: There exists an N-node network with layout area O(N log/sup 2/ N) which can emulate any N-node planar network with O(loglogN) slowdown. The N-node butterfly (and hypercube) can emulate any network with VLSI layout area N/sup 2-/spl epsiv// (/spl epsiv/>0) with O(loglogN) slowdown. We also discuss sublogarithmic bounds for the slowdown of emulations of arbitrary bounded degree networks.
INDEX TERMS
arbitrary bounded degree networks, universal emulations, sublogarithmic slowdown, bounded degree networks, butterfly, area-universal network, VLSI layout area, N-node network, hypercube, sublogarithmic bounds
CITATION

D. Krizanc, S. Rao and C. Kaklamanis, "Universal emulations with sublogarithmic slowdown," Proceedings of 1993 IEEE 34th Annual Foundations of Computer Science(FOCS), Palo Alto, CA, USA, 1993, pp. 341-350.
doi:10.1109/SFCS.1993.366853
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