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2016 International Conference on Frontiers of Information Technology (FIT) (2016)
Islamabad, Pakistan
Dec. 19, 2016 to Dec. 21, 2016
ISBN: 978-1-5090-5300-1
pp: 13-17
Aditya Rachman Putra , Department of Electrical Engineering, Institut Teknologi Bandung, Jl. Ganesha 10 Bandung 40132, West Java - Indonesia
Fadhil Mochammad , Department of Electrical Engineering, Institut Teknologi Bandung, Jl. Ganesha 10 Bandung 40132, West Java - Indonesia
Hans Herdian , Department of Electrical Engineering, Institut Teknologi Bandung, Jl. Ganesha 10 Bandung 40132, West Java - Indonesia
ABSTRACT
This paper presents a Sum of Absolute Difference (SAD) algorithm implementation in FPGA for the purpose of template matching on two binary images, and evaluates its performance. This SAD processor was implemented as a hardware unit that is capable of calculating 40 × 40 pixels at once, called a 40 × 40 SAD unit. The target and template images processed using this unit were both binary image with size of 640 × 480 and 40 × 40 respectively. In order to obtain the said images, some preprocessing is needed such as converting image from color to grayscale, calculating black threshold value, and also converting from grayscale to binary using the resulting threshold. Both images were inserted explicitly inside the program and the result of the template matching was shown using marker on a monitor. Before implementing on FPGA board the algorithm was tested on ALTERA Quartus II simulator. From the synthesis and compilation process, it was observed that this design consumed 12,075 logic elements and 332,800 of FPGA block memory. Also, this design needed 1 185 002 clock cycle to complete template matching process and. When this system clocked with 50 MHz clock, it was able to process image with speed 42.194 frames per second. The implementation of Altera DE2 on this design development board resulted on the maximum frequency 57.847 MHz.
INDEX TERMS
template matching, FPGA, SAD
CITATION
Aditya Rachman Putra, Fadhil Mochammad, Hans Herdian, "FPGA implementation of template matching using binary sum of absolute difference", 2016 International Conference on Frontiers of Information Technology (FIT), vol. 00, no. , pp. 13-17, 2016, doi:10.1109/FIT.2016.7857510
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