2015 13th International Conference on Frontiers of Information Technology (FIT) (2015)
Dec. 14, 2015 to Dec. 16, 2015
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FIT.2015.18
Many digital systems provide multiple but similar functionalities, not all of them are required simultaneously. Dedicated hardware solution for each functionality will waste too much area. This work presents a method to generate an optimized hardware solution for a set of functionalities which will execute only one functionality at a time. This single hardware solution, termed as "Multi-Circuit", shares its resources efficiently amongst multiple functionalities. Multi-Circuit is generated by initially mapping a given set of application functionalities on a common reconfigurable platform. Later all the unused logic and routing resources are removed from the reconfigurable hardware. Experiments reveal that Multi-Circuit is upto 43% smaller than the previously proposed technique named ASIF using LUT-4 architecture. Multi-Circuit is upto 89% smaller than its corresponding FPGA.
Routing, Field programmable gate arrays, Computer architecture, Hardware, Optimization, Random access memory, Software,Resource Sharing, Shared Hardware design, Area Optimization
Muhammad Mazher Iqbal, Husain Parvez, "Automatic Generation of a Shared Hardware Design for Multiple Application Circuits", 2015 13th International Conference on Frontiers of Information Technology (FIT), vol. 00, no. , pp. 35-40, 2015, doi:10.1109/FIT.2015.18