2014 12th International Conference on Frontiers of Information Technology (FIT) (2014)
Dec. 17, 2014 to Dec. 19, 2014
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FIT.2014.49
Advanced Encryption Standard (AES) is the most widely used public cipher algorithm for crypto related applications in embedded systems. This paper presents an area efficient 16-bit AES architecture for key expansion, encryption and decryption. In the proposed design, a modular approach is adopted and it is capable of performing all transformations for 128, 192 and 256-bit cipher key lengths. The resources are reduced by minimizing the slice registers and BRAMs without compromising the throughput. The slice count is cut down by sharing the hardware logic resources. Instead of using separate memories for plain text, cipher text and intermediate results, only one BRAM is used. Also for cipher key and round keys, single BRAM is incorporated. The design is synthesized and implemented using Xilinx Virtex-5 FPGA. A comparison is made with existing architectures of different datapaths.
Encryption, Ciphers, Throughput, Hardware, Field programmable gate arrays, Computer architecture, Registers
I. Ali, G. Raja and A. K. Khan, "A 16-Bit Architecture of Advanced Encryption Standard for Embedded Applications," 2014 12th International Conference on Frontiers of Information Technology (FIT), Islamabad, Pakistan, 2014, pp. 220-225.