2014 12th International Conference on Frontiers of Information Technology (FIT) (2014)
Dec. 17, 2014 to Dec. 19, 2014
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FIT.2014.44
This paper presents a new method for sizing the transistors in CMOS gates as an enabling technique for green technology. The technique utilizes an efficient feedback-based system to optimize the transistors sizes in the gates with the fanins of 2 or more. The optimized NAND2-4 gates provide nearly 65% savings in power dissipation and 58% reduction in energy consumption, as compared to their normal, uniformly sized counterparts. Power and energy savings for NOR2-4 gates are up to 8% and 38%, respectively.
Logic gates, Transistors, CMOS integrated circuits, Noise, Delays, Very large scale integration, Integrated circuit modeling
A. Beg, "Automating the CMOS Gate Sizing for Reduced Power/Energy," 2014 12th International Conference on Frontiers of Information Technology (FIT), Islamabad, Pakistan, 2014, pp. 193-196.