Frontiers of Information Technology (2013)
Islamabad, Pakistan Pakistan
Dec. 16, 2013 to Dec. 18, 2013
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FIT.2013.38
With latest advancements in architecture, reprogram ability and availability of abundant on-chip resources, FPGAs (Field Programmable Gate Array) are used as hardware accelerators to speedup computationally intensive tasks with inherent parallelism. However non-availability of standard MATLAB and C/C++ computation routines and communication interface for general purpose programming restricted researchers and developers from easily utilizing the parallel computational ability of FPGAs in MATLAB and C/C++. In this article we propose a proof of concept implementation for software-hardware co-design that can be used with MATLAB and C/C++ to share the burden of intensified computing with the FPGA. Typical applications which can be divided into multiple tasks to be executed in parallel can be easily transferred to FPGA by utilizing the proposed method. Some of the applications which can efficiently use this concept are image processing, video processing, data encryption and data compression. Results obtained by using our method and routines implemented in software and hardware provide 50% to 100% computational acceleration, as compared to routines running in software on MATLAB running on a computer. The design and concept can aid developers to use FPGAs in combination with higher level computational languages such as MATLAB and C/C++.
Field programmable gate arrays, MATLAB, Hardware, Acceleration, Computer architecture, Libraries
R. Rasul et al., "FPGA Accelerated Computing Platform for MATLAB and C/C++," 2013 11th International Conference on Frontiers of Information Technology (FIT), Islamabad, Pakistan, 2014, pp. 166-171.