Frontiers of Information Technology (2012)
Islamabad, Pakistan Pakistan
Dec. 17, 2012 to Dec. 19, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FIT.2012.45
Due to the requirement of high throughput architecture for encrypted channels, an efficient implementation of hardware is needed. This can be achieved by using smart utilization of high end reconfigurable platforms. To achieve convincingly high throughput, an efficient non-pipelined style implementation of Advanced Encryption Standard (AES) with key size of 128-bit, for multigigabit protocols on Field Programmable Gate Array (FPGA)is presented.
HDL, FPGA, AES, CBC, ECB, Multi-gigabit
Ulfat Hussain, Habibullah Jamal, "An Efficient High Throughput FPGA Implementation of AES for Multi-gigabit Protocols", Frontiers of Information Technology, vol. 00, no. , pp. 215-218, 2012, doi:10.1109/FIT.2012.45