2011 Workshop on Fault Diagnosis and Tolerance in Cryptography (2011)
Sept. 29, 2011 to Sept. 29, 2011
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FDTC.2011.19
In this contribution, we present an FPGA-based simulation environment for fault attacks on cryptographic hardware designs. With our methodology, we are able to simulate the effects of global fault attacks from e.g., spikes and local attacks from e.g., focused laser beams. The environment simulates transient bit-flip faults in sequential elements of a digital design. In this way it is tailored to the simulation of fault attacks on cryptographic designs. It is a tool to verify the design's behaviour in case of fault attacks and to verify implemented countermeasures. The environment is script-based for fully automated modification of the digital design and simulation. It can handle designs in VHDL as well as in Verilog language and does not require modifications to the design's source code. We used our environment in a case study and successfully tested the effectiveness of a fault detection countermeasure in an elliptic curve cryptography design.
fault attack, cryptographic implementations simulation, FPGA, low-cost, Xilinx, ECC case study
A. Janning, F. Stumpf, J. Heyszl and G. Sigl, "A Cost-Effective FPGA-based Fault Simulation Environment," 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography(FDTC), Tokyo, Japan, 2011, pp. 21-31.